AT89LP51RD2 Atmel Corporation, AT89LP51RD2 Datasheet - Page 157

• Manufacturer Part Number: AT89LP51RD2
• Manufacturer: Atmel Corporation

Specifications of AT89LP51RD2

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 42
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Adc Channels: 7
• Adc Resolution (bits): 10
• Adc Speed (ksps): 153.8
• Sram (kbytes): 2.25
• Self Program Memory: API
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 4
• Isp: SPI/OCD/UART
• Watchdog: Yes

.
Table 19-9.
19.6.5
3714A–MICRO–7/11
Status
Code
(SSCS)
A8h
B0h
B8h
C0h
C8h
Miscellaneous States
Status of the Two-wire
Serial Bus and Two-wire
Serial Interface Hardware
Own SLA+R has been
received; ACK has been
returned
Arbitration lost in SLA+R/W
as master; own SLA+R has
been received; ACK has
been returned
Data byte in SSDAT has
been transmitted; ACK has
been received
Data byte in SSDAT has
been transmitted; NOT ACK
has been received
Last data byte in SSDAT has
been transmitted (AA = “0”);
ACK has been received
Status Codes for Slave Transmitter Mode
There are two status codes that do not correspond to a defined TWI state, see
Status F8h indicates that no relevant information is available because the SI flag is not set. This
occurs between other states, and when the TWI is not involved in a serial transfer.
Status 00h indicates that a bus error has occurred during a Two-wire Serial Bus transfer. A bus
error occurs when a START or STOP condition occurs at an illegal position in the format frame.
To/from SSDAT
Load data byte
Load data byte
Load data byte
Load data byte
Load data byte
Load data byte
No action
No action
No action
No action
No action
No action
No action
No action
Application Software Response
STA
AT89LP51RD2/ED2/ID2 Preliminary
X
X
X
X
X
X
0
0
1
1
0
0
1
1
STO
0
0
0
0
0
0
0
0
0
0
0
0
0
0
To SSCON
SI
1
1
1
1
1
1
1
1
1
1
1
1
1
1
AA
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Next Action Taken by TWI Hardware
Last data byte will be transmitted and NOT
ACK should be received
Data byte will be transmitted and ACK should
be received
Last data byte will be transmitted and NOT
ACK should be received
Data byte will be transmitted and ACK should
be received
Last data byte will be transmitted and NOT
ACK should be received
Data byte will be transmitted and ACK should
be received
Switched to the not addressed Slave mode; no
recognition of own SLA or GCA
Switched to the not addressed Slave mode;
own SLA will be recognized; GCA will be
recognized if GC = “1”
Switched to the not addressed Slave mode; no
recognition of own SLA or GCA; a START
condition will be transmitted when the bus
becomes free
Switched to the not addressed Slave mode;
own SLA will be recognized; GCA will be
recognized if GC = “1”; a START condition will
be transmitted when the bus becomes free
Switched to the not addressed Slave mode; no
recognition of own SLA or GCA
Switched to the not addressed Slave mode;
own SLA will be recognized; GCA will be
recognized if GC = “1”
Switched to the not addressed Slave mode; no
recognition of own SLA or GCA; a START
condition will be transmitted when the bus
becomes free
Switched to the not addressed Slave mode;
own SLA will be recognized; GCA will be
recognized if GC = “1”; a START condition will
be transmitted when the bus becomes free
Table
19-10.
157