AT89LP51 Atmel Corporation, AT89LP51 Datasheet - Page 33

• Manufacturer Part Number: AT89LP51
• Manufacturer: Atmel Corporation

Specifications of AT89LP51

• Flash (kbytes): 4 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 36
• Uart: 1
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI
• Watchdog: Yes

7.2
7.3
3709D–MICRO–12/11
Brown-out Reset
External Reset
Table 7-1.
The AT89LP51/52 has an on-chip Brown-out Detection (BOD) circuit for monitoring the V
during operation by comparing it to a fixed trigger level. The trigger level V
nominally 2.0V. The purpose of the BOD is to ensure that if V
speed, the system will gracefully enter reset without the possibility of errors induced by incorrect
execution. A BOD sequence is shown in
trigger level V
trigger level plus about 200 mV of hysteresis, the start-up timer releases the internal reset after
the specified time-out period has expired
Figure 7-2.
The AT89LP51/52 allows for a wide V
cient to prevent incorrect execution if V
as when a 5.0V supply is coupled with high frequency operation. In such cases an external
Brown-out Reset circuit connected to the RST pin may be required.
The RST pin of the AT89LP51/52 can function as either an active-low reset input or as an active-
high reset input. The polarity of the RST pin is selectable using the POL pin (formerly EA). When
POL is high the RST pin is active high with an on-chip pull-down resistor tied to GND. When
POL is low the RST pin is active low with an on-chip pull-up resistor tied to V
structure is shown in
cycles and must be held active for at least twelve clock cycles to trigger the internal reset. In
Fast mode the reset pin is sampled every clock cycle and must be held active for at least two
clock cycles to trigger the internal reset.
Time-out
SUT Fuse 1
Internal
Reset
V
0
0
1
1
DD
BOD
Start-up Timer Settings
Brown-out Detector Reset
V POR
, the internal reset is immediately activated. When V
SUT Fuse 0
Figure
0
1
0
1
7-3. In Compatibility mode the reset pin is sampled every six clock
Clock Source
Internal RC/External Clock
Crystal Oscillator
Internal RC/External Clock
Crystal Oscillator
Internal RC/External Clock
Crystal Oscillator
Internal RC/External Clock
Crystal Oscillator
DD
BOD
Figure
(Table
operating range. The on-chip BOD may not be suffi-
is lower than the minimum required V
V BOD
t SUT
7-2. When V
7-1).
DD
DD
decreases to a value below the
fails or dips while executing at
AT89LP51/52
DD
increases above the
BOD
t
SUT
DD
DD
for the BOD is
. The RST pin
16384
(± 5%) µs
1024
2048
1024
4096
4096
512
16
range, such
DD
level
33