AT89LP51 Atmel Corporation, AT89LP51 Datasheet

Page 1

... Input-only (Tristate) • Push-pull CMOS Output • Open-drain • Operating Conditions – 2.4V to 5.5V V Voltage Range CC – -40° 85°C Temperature Range – MHz @ 2.4V–5.5V – MHz @ 4.5V–5.5V 8-bit Microcontroller with 4K/8K Bytes In-System Programmable Flash AT89LP51 AT89LP52 3709D–MICRO–12/11 ...

Page 2

... Pin Configurations 1.1 40-lead PDIP 1.2 44-lead TQFP (MOSI) P1.5 (MISO) P1.6 AT89LP51/52 2 (T2) P1 VCC (T2 EX) P1 P0.0 (AD0) P1 P0.1 (AD1) P1 P0.2 (AD2) P1 P0.3 (AD3) (MOSI) P1 P0.4 (AD4) (MISO) P1 P0.5 (AD5) (SCK) P1 P0.6 (AD6) RST 9 32 P0.7 (AD7) (RXD) P3 POL (TXD) P3 P4.2 (ALE) (INT0) P3 ...

Page 3

... P3.1 13 (INT0) P3.2 14 (INT1) P3.3 15 (T0) P3.4 16 (T1) P3.5 17 MOSI/P1.5 1 MISO/P1.6 2 SCK/P1.7 3 RST 4 RXD/P3.0 5 *NC 6 TXD/P3.1 7 INT0/P3.2 8 INT1/P3.3 9 T0/P3.4 10 T1/P3.5 11 NOTE: Bottom pad should be soldered to ground AT89LP51/52 39 P0.4 (AD4) 38 P0.5 (AD5) 37 P0.6 (AD6) 36 P0.7 (AD7) 35 POL 34 *NC 33 P4.4 (ALE) 32 P4.5 (PSEN) 31 P2.7 (A15) 30 P2.6 (A14) 29 P2.5 (A13) 33 P0.4/AD4 32 P0.5/AD5 31 P0.6/AD6 30 P0.7/AD7 29 POL 28 *NC 27 P4.4/ALE 26 P4 ...

Page 4

... Pin Description Table 1-1. AT89LP51/52 Pin Description Pin Number TQFP PLCC PDIP VQFN ...

Page 5

... Table 1-1. AT89LP51/52 Pin Description Pin Number TQFP PLCC PDIP VQFN ...

Page 6

... The device is manufactured using Atmel's high-density nonvolatile memory technology and is compatible with the industry-standard 80C52 instruction set. The AT89LP51/52 is built around an enhanced CPU core that can fetch a single byte from mem- ory every clock cycle. In the classic 8051 architecture, each fetch requires 6 clock cycles, forcing instructions to execute in 12 clock cycles ...

Page 7

... Port 1 Configurable I/O Port 2 Configurable I/O Port 3 Configurable I/O Port 4 Configurable I/O Configurable Oscillator lists the fusable options for the AT89LP51/52. These options maintain their state even Section 17.7 “User Configuration Fuses” on page AT89LP51/52 256 Bytes XRAM RAM Interface UART 16-bit Timer 0 16-bit Timer 1 16-bit Timer 2 ...

Page 8

... IAP 2.3 Comparison to AT89S51/52 The AT89LP51/52 is part of a family of devices with enhanced features that are fully binary com- patible with the 8051 instruction set. The AT89LP51/52 has two modes of operations, Compatibility mode and Fast mode. In Compatibility mode the instruction timing, peripheral behavior, SFR addresses, bit assignments and pin functions are identical to Atmel's existing AT89S51/52 product ...

Page 9

... Reset The RST pin of the AT89LP51/52 has selectable polarity using the POL pin (formerly EA). When POL is high the RST pin is active high with a pull-down resistor and when POL is low the RST pin is active low with a pull-up resistor. For existing AT89S51/52 sockets where EA is tied to VDD, replacing AT89S51/52 with AT89LP51/52 will maintain the active high reset ...

Page 10

... I/O Ports The P0, P1, P2 and P3 I/O ports of the AT89LP51/52 may be configured in four different modes. The default setting depends on the Tristate-Port User Fuse (See When the fuse is set all the I/O ports revert to input-only (tristated) mode at power-up or reset. When the fuse is not active, ports P1, P2 and P3 start in quasi-bidirectional mode and P0 starts in open-drain mode ...

Page 11

... The program memory has a regular linear address space with support for 64K bytes of directly addressable application code. The data memory has 256 bytes of internal RAM and 128 bytes of Special Function Register I/O space. The AT89LP51/52 supports up to 64K bytes of external data memory, with portions of the external data memory space implemented on chip as nonvolatile Flash data memory ...

Page 12

... External Program Memory Interface The AT89LP51/52 uses the standard 8051 external program memory interface with the upper address on Port 2, the lower address and data in/out multiplexed on Port 0, and the ALE and PSEN strobes. Program memory addresses are always 16-bits wide, even though the actual amount of program memory used may be less than 64K byes ...

Page 13

... SIG In addition to the 64K code space, the AT89LP51/52 also supports a 256-byte User Signature Array and a 128-byte Atmel Signature Array that are accessible by the CPU. The Atmel Signa- ture Array is initialized with the Device ID in the factory. The User Signature Array is available for user identification codes or constant parameter data. Data stored in the signature array is not secure. Security bits will disable writes to the array ...

Page 14

... Internal Data Memory The AT89LP51/52 contains 256 bytes of general SRAM data memory plus 128 bytes of I/O memory mapped into a single 8-bit address space. Access to the internal data memory does not require any configuration. The internal data memory has three address spaces: DATA, IDATA and SFR ...

Page 15

... CPU can access them. The AT89LP51/52 includes 256 bytes of nonvolatile Flash data memory (FDATA). 3.3.1 XDATA The external data memory space can accommodate up to 64KB of external memory. The AT89LP51/52 uses the standard 8051 external data memory interface with the upper address byte on Port 2, the lower address byte and data in/out multiplexed on Port 0, and the ALE, RD and WR strobes ...

Page 16

... The AT89LP51/52 includes 2 data pages of 128 bytes each. One or more bytes in a page may be written at one time. The AT89LP51/52 includes a temporary page buffer of 64 bytes, or half of a page. Because the page buffer is 64 bytes long, the maximum number of bytes written at one time is 64. Therefore, two write cycles are required to fill the entire 128-byte page, one for the low half page (00H– ...

Page 17

... Then the modified bytes of the low half page are stored 3709D–MICRO–12/11 Figures 3-8 and Figure 3-9 on page 17 FDATA Byte Write DMEN MWEN LDPG IDLE t WC MOVX FDATA Page Write DMEN MWEN LDPG IDLE MOVX AT89LP51/52 show the difference between byte ...

Page 18

... External Data Memory Interface The AT89LP51/52 uses the standard 8051 external data memory interface with the upper address on Port 2, the lower address and data in/out multiplexed on Port 0, and the ALE, RD and WR strobes. The interface may be used in two different configurations depending on which type of MOVX instruction is used to access XDATA ...

Page 19

... RAM AT89LP P1 P0 ALE I/O WR Section 10.1 “Port Configuration” on page and Figure 3-13 show examples of external data memory write and read cycles, Section 6.4 on page 31). AT89LP51/52 EXTERNAL DATA MEMORY DATA LATCH ADDR WE OE EXTERNAL DATA MEMORY DATA LATCH ADDR PAGE ...

Page 20

... AUXR.4 and AUXR.3 function as WDIDLE and DISRTO only in Compatibility mode. In Fast mode these bits are located in WDTCON. 2. WS1 is only available in Fast mode. WS1 is forced Compatibility mode. Figure 3-12. Fast Mode External Data Memory Write Cycle (WS = 00B) CLK AT89LP51/52 20 DISRTO (1) – WDIDLE ...

Page 21

... WR DPL SFR OUT PCH SFR CLK ALE RD DPL SFR OUT PCH SFR AT89LP51/ DATA SAMPLED FLOAT DPH or P2 OUT PCL or DATA OUT P0 SFR PCH or DPH or P2 OUT P2 SFR DATA SAMPLED ...

Page 22

... P0 Figure 3-17. MOVX with Two Wait States (WS = 10B) CLK ALE Figure 3-18. MOVX with Three Wait States (WS = 11B) CLK ALE AT89LP51/ SFR DPH or P2 OUT P0 SFR DPL OUT DATA OUT FLOAT P0 SFR DPL OUT ...

Page 23

... In-Application Programming (IAP) The AT89LP51/52 supports In-Application Programming (IAP), allowing the program memory to be modified during execution. IAP can be used to modify the user application on the fly or to use program memory for nonvolatile data storage. The same page structure write protocol for FDATA also applies to IAP (See always placed in idle while modifying the program memory ...

Page 24

... Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. User software should not write to these unlisted locations, since they may be used in future products to invoke new features. Table 4-1. AT89LP51/52 SFR Map and Reset Values 8 9 0F8H ...

Page 25

... Enhanced CPU The AT89LP51/52 uses an enhanced 8051 CPU that runs times the speed of standard 8051 devices ( times the speed of X2 8051 devices). The increase in performance is due to two factors. First, the CPU fetches one instruction byte from the code memory every clock cycle ...

Page 26

... Enhanced Dual Data Pointers The AT89LP51/52 provides two 16-bit data pointers: DPTR0 formed by the register pair DPOL and DPOH (82H an 83H), and DPTR1 formed by the register pair DP1L and DP1H (84H and 85H). The data pointers are used by several instructions to access the program or data memo- ries ...

Page 27

... Data Pointer Update The Dual Data Pointers on the AT89LP51/52 include two features that control how the data pointers are updated. The data pointer decrement bits, DPD1 and DPD0 in AUXR1, configure the INC DPTR instruction to act as DEC DPTR. The resulting operation will depend on DPS as shown in MOVX ...

Page 28

... The direction of update depends on the DPD1 and DPD0 bits as shown in 5-4. These bits can be used to make block copy routines more efficient. Table 5-4. DPD1 AT89LP51/52 28 Data Pointer Decrement Behavior Equivalent Operation for INC DPTR and INC /DPTR DPS = 0 DPD0 INC DPTR INC /DPTR ...

Page 29

... Fuse applies for both high and low power oscillators. Note that in some cases, external AT89LP51/52 Figure 6-1. The on-chip crystal oscillator may also be “User Configuration Fuses” on page “Reset” on page 32 5-BIT CLOCK DIVIDER 4-BIT ...

Page 30

... I/O P4.7, or configured to output a divided version of the system clock. Figure 6-3. 6.3 Internal RC Oscillator The AT89LP51/52 has an Internal Auxiliary oscillator tuned to 1.8432 MHz ±2.0%. When enabled as the clock source, XTAL1 and XTAL2 may be used as P4.6 and P4.7 respectively. AT89LP51/52 30 Crystal Oscillator Connections ...

Page 31

... The clock divider will prescale the clock OSC OSC TPS1 TPS0 5 4 CDIV0 System Clock Frequency OSC OSC OSC OSC 0 f /16 OSC 1 f /32 OSC 0 Reserved 1 Reserved AT89LP51/52 f OSC = ------------ - f SYS CDV 2 . Reset Value = 0?0? 00?0B CDV2 CDV1 CDV0 — ...

Page 32

... During reset, all I/O Registers are set to their initial values, the port pins are set to their default mode, and the program starts execution from the Reset Vector, 0000H. The AT89LP51/52 has five sources of reset: power-on reset, brown-out reset, external reset, watchdog reset, and soft- ware reset ...

Page 33

... External Reset The RST pin of the AT89LP51/52 can function as either an active-low reset input active- high reset input. The polarity of the RST pin is selectable using the POL pin (formerly EA). When POL is high the RST pin is active high with an on-chip pull-down resistor tied to GND. When ...

Page 34

... The AT89LP51/52 includes an on-chip Power-On Reset and Brown-out Detector circuit that ensures that the device is reset from system power up. In most cases a RC startup circuit is not required on the RST pin, reducing system cost, and the RST pin may be left unconnected if a board-level reset is not present. ...

Page 35

... RAM contents will be retained, but the SFR contents are not guaranteed once V reduced. Power-down may be exited by external reset, power-on reset, or certain enabled interrupts. 3709D–MICRO–12/11 (Section 6.4 on page PWDEX POF GF1 AT89LP51/52 31). Be aware that the clock divider Reset Value = 000X 0000B GF0 PD IDL has been DD ...

Page 36

... CPU until after the timer has timed out. The time-out period is controlled by the Start-up Timer Fuses. (See clock cycle internal reset is generated when the internal clock restarts. Otherwise, the device will remain in reset until RST is brought low. AT89LP51/52 36 Interrupt Recovery from Power-down (PWDEX = 1) t SUT ...

Page 37

... DISALE in AUXR, thereby also reducing EMI. 9. Interrupts The AT89LP51/52 provides 6 interrupt sources: two external interrupts, three timer interrupts, and a serial port interrupt. These interrupts and the system reset each have a separate program vector at the start of the program memory space. Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable register IE ...

Page 38

... If the instruction in progress is not in its final clock cycle, the additional wait time cannot be more than 4 cycles, since the longest AT89LP51/52 38 Interrupt Vector Addresses ...

Page 39

... INT0 Ack. IE0 Instruction LCALL Figure 9-4. Maximum Interrupt Response Time (Compatibility Mode) 1 Clock Cycles INT0 IE0 Instruction RETI 3709D–MICRO–12/11 9-2. 5 LCALL 1st ISR Instr Ack. MOVX @/DPTR, A LCALL 14 ISR 13 Ack. MUL AB AT89LP51/52 14 1st ISR Instr LCALL ISR Figure 9-1 39 ...

Page 40

... Symbol Function PT2H Timer 2 Interrupt Priority High PSH Serial Port Interrupt Priority High PT1H Timer 1 Interrupt Priority High PX1H External Interrupt 1 Priority High PT0H Timer 0 Interrupt Priority High PX0H External Interrupt 0 Priority High AT89LP51/52 40 ET2 ES ET1 PT2 PS PT1 PT2H ...

Page 41

... I/O Ports The AT89LP51/52 can be configured for between 32 and 36 I/O pins. The exact number of I/O pins available depends on the clock, external memory and package type as shown in 1. Table 10-1. Clock Source External Crystal or Resonator External Clock Internal RC Oscillator 10.1 Port Configuration Each 8-bit port on the AT89LP51/52 may be configured in one of four modes: quasi-bidirectional (standard 8051 port outputs), push-pull output, open-drain output, or input-only ...

Page 42

... Power-down when configured in this mode. Input-only mode can reduce power consumption for low-level inputs over quasi-bidirectional mode because the “very weak” pull-up is turned off and only very small leakage current in the sub microamp range is present. AT89LP51/52 42 P2M1 P2M0 ...

Page 43

... F rom Register Input Data PWD Input Data Figure 10-4. The input circuitry of P3.2, P3.3, P4.6 and P4.7 is not disabled Figure 10-3) and therefore these pins should not be left floating during F rom Register AT89LP51/ Strong Input Data ...

Page 44

... Mnemonic ANL ORL XRL JBC CPL INC DEC DJNZ MOV PX.Y, C CLR PX.Y SETB PX.Y AT89LP51/52 44 Input Data PWD for a complete list of Read-Modify-Write instruction which may access the ports. Port Read-Modify-Write Instructions Instruction Logical AND Logical OR Logical EX-OR Jump if bit set and clear bit Complement bit ...

Page 45

... Port Alternate Functions Most general-purpose digital I/O pins of the AT89LP51/52 share functionality with the various I/Os needed for the peripheral units. Alternate functions are connected to the pins in a logic AND fashion. In order to enable the alternate function on a port pin, that pin must have a “1” in its corresponding port register bit, otherwise the input/output will always be “ ...

Page 46

... Timer 0 and Timer 1 The AT89LP51/52 has two 16-bit Timer/Counters, Timer 0 and Timer 1, with the following features: • Two independent 16-bit timer/counters with 8-bit reload registers • UART baud rate generation using Timer 1 • Output pin toggle on timer overflow • Split timer mode allows for three separate timers (2 8-bit, 1 16-bit) • ...

Page 47

... C C Pin Control TR1 GATE1 INT1 Pin Mode 1: Time-out Period ÷CDV ÷TPS C C Pin Control TR1 GATE1 INT1 Pin AT89LP51/52 Figure 11-1 8192 × ------------------------------------------------- - TPS System Frequency TL1 TH1 TF1 (5 Bits) (8 Bits) Figure 11-1. There are two different C/T bits, 65536 × ...

Page 48

... Mode 3 is for applications requiring an extra 8-bit timer or counter. With Timer 0 in Mode 3, the AT89LP51/52 can appear to have four Timer/Counters. When Timer Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3. In this case, Timer 1 can still be used by the serial port as a baud rate generator or in any application not requiring an interrupt ...

Page 49

... Clock Output (Pin Toggle Mode) On the AT89LP51/52, Timer 0 and Timer 1 may be independently configured to toggle their respective counter pins, T0 and T1, on overflow by setting the T0OE or T1OE bits in TCONB. The C/Tx bits must be set to “0” when in toggle mode and the T0 (P3.4) and T1 (P3.5) pins must be configured in an output mode ...

Page 50

... AT89LP51/52 50 T1M1 T1M0 GATE0 Operation 13-bit Timer Mode. 8-bit Timer/Counter TH1 with TL1 as 5-bit prescaler. 16-bit Timer Mode. TH1 and TL1 are cascaded to form a 16-bit Timer/Counter. 8-bit Auto Reload Mode. TH1 holds a value which is reloaded into 8-bit Timer/Counter TL1 each time it overflows ...

Page 51

... Timer 2 The AT89LP51/52 includes a 16-bit Timer/Counter 2 with the following features: • 16-bit timer/counter with one 16-bit reload/capture register • One external reload/capture input • Up/Down counting mode with external direction control • UART baud rate generation • Output-pin toggle on timer overflow • ...

Page 52

... Timer 2 Output Enable. When T2OE = 1 and C/ the T2 pin will toggle after every Timer 2 overflow. DCEN Timer 2 Down Count Enable. When Timer 2 operates in Auto-Reload mode and EXEN2 = 1, setting DCEN = 1 will cause Timer 2 to count up or down depending on the state of T2EX. AT89LP51/52 52 Table 12-4). The register pair {TH2, TL2} at addresses 0CDH and 0CCH are the ...

Page 53

... Summary of Auto-Reload Modes T2EX Direction Behavior X Up BOTTOM → 0 Down MAX BOTTOM 1 Up BOTTOM shows Timer 2 automatically counting up when DCEN = 0. In this mode Timer 2 Time-out Period DCEN = 0 AT89LP51/52 65536 × ( ------------------------------------------------- - TPS = System Frequency TL2 TH2 TF2 O VERFLO W RCAP2H TIMER 2 INTERR UPT EXF2 Table 12-5. ...

Page 54

... In this operating mode, EXF2 does not flag an interrupt. The behavior of Timer 2 when DCEN is enabled is shown in Figure 12-4. Timer 2 Waveform: Auto-Reload Mode (DCEN = 1) MAX BOTTOM MIN T2EX EXF2 AT89LP51/52 54 TL2 TH2 = 00B, the timer will overflow at MAX and set the TF2 bit. This overflow 1-0 TF2 Set Figure 12-5 ...

Page 55

... T2EX can be used as an extra external interrupt. Also note that the Baud Rate and Frequency Generator modes may be used simultaneously. 3709D–MICRO–12/11 Modes 1 and 3 Baud Rates = Modes 1, 3 System Frequency = -------------------------------------------------------------------------------------------------------------------------------- - × × TPS 1 + Baud Rate Figure AT89LP51/52 Figure 12-6. Timer 2 Overflow Rate ----------------------------------------------------------- - 65536 RCAP2H,RCAP2L – 12-6. This figure is valid only if RCLK or (Table 55 ...

Page 56

... Note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L. Figure 12-7. Timer 2 in Clock-out Mode OSC T2 PIN T2EX PIN AT89LP51/ TL2 TH2 TR2 C/ ...

Page 57

... External Interrupts The INT0 (P3.2) and INT1 (P3.3) pins of the AT89LP51/52 may be used as external interrupt sources. The external interrupts can be programmed to be level-activated or transition-activated by setting or clearing bit IT1 or IT0 in Register TCON. If ITx = 0, external interrupt x is triggered by a detected low at the INTx pin. If ITx = 1, external interrupt x is edge-triggered. In this mode if successive samples of the INTx pin show a high in one cycle and a low in the next cycle, inter- rupt request flag IEx in TCON is set ...

Page 58

... Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the RI other modes, in any serial reception (except see SM2). Must be cleared by software. Notes: 1. SMOD0 is located at PCON. system frequency. The baud rate depends on SMOD1 (PCON.7). SYS AT89LP51/52 58 SM2 REN TB8 ...

Page 59

... See “Automatic Address Recognition” on page 61. SMOD1 Mode 0 Baud Rate 2 × ------------------- - = 4 TB8 = 0 SMOD1 Mode 0 Baud Rate 2 × ------------------- - = 6 TB8 = 0 SMOD1 2 × ------------------- - Mode 2 Baud Rate = 32 SMOD1 Mode 0 Baud Rate 2 × ------------------- - (Timer 1 Overflow Rate TB8 = 1 AT89LP51/52 System Frequency System Frequency System Frequency 59 ...

Page 60

... Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON. Under these conditions, the baud rates for transmit and receive can be simultaneously different by using Timer 1 for transmit and Timer 2 for receive, or vice versa. The baud rate generator mode AT89LP51/52 60 SMOD1 ...

Page 61

... CDV CP/RL2 OSC 12 0 11.059 0 11.059 0 11.059 0 11.059 0 11.059 0 11.986 11.059 1 11.059 1 11.059 1 11.059 1 11.059 1 11.986 AT89LP51/52 System Frequency ( ) ] 65536 – RCAP2H,RCAP2L Timer 2 C/T2 TCLK or RCLK ...

Page 62

... Slave 2 requires that bit and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2, use address 1110 0100, since it is necessary to make bit exclude slave 2. AT89LP51/52 62 SADDR = 1100 0000 ...

Page 63

... Mode 0. Mode 0 Baud Rates SMOD1 Baud Rate (Fast SYS SYS 0 (Timer 1 Overflow (Timer 1 Overflow Table 14-5 and shown in AT89LP51/52 Baud Rate (Compatibility SYS f /3 SYS (Timer 1 Overflow (Timer 1 Overflow Figure . The SM2 bit determines the idle Fig- 63 ...

Page 64

... RXD (TX) RXD (RX) SMOD1 = 1 TXD SM2 = 1 RXD (TX) RXD (RX) Figure 14-2. UART Mode 0 TWI Emulation (SMOD1 = 1) (SCL) TXD 0 (SDA) RXD SM2 P3.0 Write to SBUF TI AT89LP51/52 64 Mode 0 Clock and Data Modes SMOD1 Clock Idle 0 High While clock is high 1 High Negative edge of clock 0 Low While clock is low 1 ...

Page 65

... SMOD1 WRITE SEND SHIFT RXD ( OUT ) TXD (SHIFT CLOCK) TI WRITE T O SCON (CLEAR RECEIVE SHIFT RXD ( TXD (SHIFT CLOCK) 3709D–MICRO–12/11 INTERNAL “1“ INTERNAL AT89LP51/52 SM2 65 ...

Page 66

... SPI slave devices as shownin UART hardware between SPI devices connected on P1 and UART devices on P3 with the caveat that any asynchronous receptions on the RXD pin will be ignored while the UART is in Mode 0. Figure 14-4. SPI Connections for UART Mode 0 AT89LP51/52 66 MOV R7 ...

Page 67

... WRITE SEND SHIFT MOSI (DATA OUT) SCK (SHIFT CLOCK) MISO (DATA IN 3709D–MICRO–12/11 INTERNAL BUS “1“ TI SERIAL PORT INTERRUPT INTERNAL AT89LP51/52 MOSI P1.5 ALT OUTPUT FUNCTION SCK P1.7 ALT SM2 OUTPUT FUNCTION MISO P1.6 ALT OUTPUT FUNCTION 67 ...

Page 68

... On receive, the stop bit goes into RB8 in SCON. In the AT89LP51/52, the baud rate is determined either by the Timer 1 overflow rate, the TImer 2 over- flow rate, or both. In this case one timer is for transmit and the other is for receive. ...

Page 69

... RX CLOCK SEND TI TI SERIAL PORT ÷16 LOAD RX CLOCK RI SBUF START RX CONTROL SHIFT 1FFH BIT DETECTOR INPUT SHIFT REG. (9 BITS) LOAD SBUF SBUF READ SBUF INTERNAL BUS AT89LP51/52 TXD SHIFT D6 D7 STOP BIT STOP BIT 69 ...

Page 70

... SBUF. One bit time later, whether the above conditions were met or not, the unit continues look- ing for a 1-to-0 transition at the RXD input. Note that the value of the received stop bit is irrelevant to SBUF, RB8, or RI. AT89LP51/52 70 show a functional diagram of the serial port in Modes 2 and 3. The ...

Page 71

... Figure 14-7. Serial Port Mode 2 CPU CLOCK SMOD1 1 SMOD1 0 3709D–MICRO–12/11 INTERNAL BUS INTERNAL BUS AT89LP51/52 71 ...

Page 72

... CLOCK WRITE TO SBUF SEND DATA SHIFT D0 D1 TXD START BIT TI STOP BIT GEN ÷16 RESET RX CLOCK RXD START BIT BIT DETECTOR SAMPLE TIMES SHIFT RI AT89LP51/52 72 INTERNAL BUS TB8 SBUF CL ZERO DETECTOR STOP BIT SHIFT DATA START TX CONTROL ÷16 RX CLOCK SEND TI ...

Page 73

... Software Reset A Software Reset of the AT89LP51/52 is accomplished by writing the software reset sequence 5AH/A5H to the WDTRST SFR. The WDT does not need to be enabled to generate the software reset. A normal software reset will set the SWRST flag in WDTCON. However any time an incorrect sequence is written to WDTRST (i ...

Page 74

... The WDT is enabled by writing the sequence 1EH/E1H to the WDTRST SFR. The current status may be checked by reading the WDTEN bit in WDTCON. To prevent the WDT from resetting the device, the same sequence 1EH/E1H must be written to WDTRST before the time-out interval expires. A software reset is generated by writing the sequence 5AH/A5H to WDTRST. AT89LP51/52 74 MOV WDTRST, #05Ah ...

Page 75

... The AT89LP51/52 is fully binary compatible with the 8051 instruction set. In Compatibility mode the AT89LP51/52 has identical execution time with AT89S51/52 and other standard 8051s. The difference between the AT89LP51/52 in Fast mode and the standard 8051 is the number of cycles required to execute an instruction. Fast mode instructions may take clock cycles to complete ...

Page 76

... ORL direct, #data XRL A, Rn XRL A, direct XRL A, @Ri XRL A, #data XRL direct, A XRL direct, #data RL A RLC RRC A SWAP A Data Transfer MOV A, Rn MOV A, direct MOV A, @Ri AT89LP51/52 76 Instruction Execution Times and Exceptions ( Bytes ...

Page 77

... Bytes AT89LP51/52 (1) (Continued – – (3) ...

Page 78

... LJMP addr16 JMP @A+DPTR JMP @A+PC CJNE A, direct, rel CJNE A, #data, rel CJNE Rn, #data, rel CJNE @Ri, #data, rel CJNE A, @R0, rel CJNE A, @R1, rel DJNZ Rn, rel DJNZ direct, rel NOP Notes: AT89LP51/52 78 Instruction Execution Times and Exceptions Bytes ...

Page 79

... SPI master, and the target system always operates as the SPI slave. To enter or remain in Programming mode the device’s reset line (RST) must be held active. With the addition of VDD and GND, an AT89LP51/52 microcontroller can be programmed with a min- imum of seven connections as shown in Figure 17-1. In-System Programming Device Connections 3709D– ...

Page 80

... The ISP interface uses the SPI clock mode 0 (CPOL = 0, CPHA = 0) exclusively with a maximum frequency of 5 MHz. • The AT89LP51/52 will enter programming mode only when its reset line (RST) is active. To simplify this operation recommended that the target reset can be controlled by the In- System programmer ...

Page 81

... Memory Organization The AT89LP51/52 offers 8K bytes of In-System Programmable (ISP) nonvolatile Flash code memory and 256 bytes of nonvolatile Flash data memory. In addition, the device contains a 256- byte User Signature Array and a 128-byte read-only Atmel Signature Array. The memory organi- zation is shown in each. A single read or write command may only access half a page (64 bytes) in the memory; ...

Page 82

... Page oriented instructions always include a full 16-bit address. The higher order bits select the page and the lower order bits select the byte within that page. The AT89LP51/52 allocates 6 bits for byte address, 1 bit for low/high half page selection and 9 bits for page address. The half page to be accessed is always fixed by the page address and half select as transmitted ...

Page 83

... X X WRITE Address High Address Low READ Address High Address Low WRITE Address High Address Low READ Address High Address Low AT89LP51/ Data Data Out Data In 0 ...

Page 84

... Parallel Enable switches the interface from serial to parallel format until RST goes inactive. 4. Each byte address selects one fuse or lock bit. Data bytes must be 00h or FFh. 5. See Table 17-5 on page 86 6. See Table 17-4 on page 86 AT89LP51/52 84 Opcode Addr High 1010 1100 0101 0011 ...

Page 85

... Flash Security The AT89LP51/52 provides three Lock Bits for Flash Code and Data Memory security. Lock bits can be left unprogrammed (FFh) or programmed (00h) to obtain the protection levels listed in Table 17-4 ...

Page 86

... User Configuration Fuses The AT89LP51/52 includes 10 user fuses for configuration of the device. Each fuse is accessed at a separate address in the User Fuse Row as listed in gramming 00h to their locations. Programming FFh to a fuse location will cause that fuse to maintain its previous state. To set a fuse (set to FFh) the fuse row must be erased and then reprogrammed using the Fuse Write with Auto-erase command ...

Page 87

... FFh: In-Application Programming Disabled 00h: In-Application Programming Enabled FFh: 5 MΩ resistor on XTAL1 Disabled 00h: 5 MΩ resistor on XTAL1 Enabled 91. 33). . and drive RST high if active-high otherwise keep low. PWRUP for the internal Power-on Reset to complete. The value of t SUT AT89LP51/52 “Tim- will SUT 87 ...

Page 88

... ISP Start Sequence Execute this sequence to exit CPU execution mode and enter ISP mode when the device has passed Power-On Reset and is already operational. 1. Drive RST high. 2. Wait t 3. Drive SCK low. 4. Start programming session. AT89LP51/ PWRUP RST RST ...

Page 89

... SCK. SSZ V DD XTAL1 RST SSD RHZ SCK MISO MOSI The waveforms on this page are not to scale. Figure 17-13. The SCK phase and polarity follow SPI clock mode 0 (CPOL = 0, AT89LP51/ RLZ STL ZSS HIGH Z HIGH Z SSZ HIGH Z HIGH Z Figure 17-14. t SSE 89 ...

Page 90

... Figure 17-13. ISP Byte Sequence Figure 17-14. Serial Programming Interface Timing RST SCK MISO MOSI Figure 17-15. Parallel Programming Interface Timing RST SCK OE P0 AT89LP51/52 90 SCK MOSI MISO Data Sampled SCK SSE t t SHSL SLSH t SOV SCK SSE ...

Page 91

... RST Inactive Lag Time SSD SCK Setup to SS Low ZSS SCK Hold after SS High SSZ Write Cycle Time WR Write Cycle with Auto-Erase Time Chip Erase Cycle Time ERS independent SCK CLCL AT89LP51/52 17-10, Figure 17-11, Figure 17-12, Min Max 100 CLCL ...

Page 92

... Power-down Mode Notes: 1. Under steady state (non-transient) conditions, I Maximum I per port pin Maximum total I for all output pins: 100 exceeds the test condition than the listed test conditions. AT89LP51/52 92 *NOTICE: Condition = 5V ± ± ...

Page 93

... Supply Current (Internal Oscillator) Figure 18-1. Active Supply Current vs. Vcc (1.8432 MHz Internal Oscillator) 3709D–MICRO–12/ ± 10% DD Active Supply Current vs. Vcc 1.8432 MHz Internal Oscillator 1.25 Compatibility Mode 1.00 0.75 0.50 0.25 2.0 2.5 3.0 3.5 Vcc (V) 3.0 Fast Mode 2.5 2.0 1.5 1.0 2.0 2.5 3.0 3.5 Vcc (V) AT89LP51/52 4.0 4.5 5.0 5.5 4.0 4.5 5.0 5.5 85C -40C 25C 85C -40C 25C 93 ...

Page 94

... Figure 18-2. Idle Supply Current vs. Vcc (1.8432 MHz Internal Oscillator) AT89LP51/52 94 Idle Supply Current vs. Vcc 1.8432 MHz Internal Oscillator 0.60 Compatibility Mode 0.45 0.30 0.15 0.00 2.0 2.5 3.0 3.5 Vcc (V) 0.8 Fast Mode 0.6 0.4 0.2 0.0 2.0 2.5 3.0 3.5 Vcc (V) 4.0 4.5 5.0 5.5 4.0 4.5 5.0 5.5 3709D–MICRO–12/11 85C -40C 25C 85C -40C 25C ...

Page 95

... Active Supply Current vs. Frequency External Clock Source 8 Compatibility Mode Frequency (MHz) 20 Fast Mode Frequency (MHz MIPS AT89LP51/ 5.5V 5.0V 4.5V 3.6V 3.0V 2.4V 5.5V 5.0V 4.5V 3.6V 3.0V 2.4V 5V Compat. 3V Compat. 5V Fast 3V Fast 95 ...

Page 96

... Figure 18-4. Idle Supply Current vs. Frequency AT89LP51/52 96 Idle Supply Current vs. Frequency External Clock Source 3.0 Compatibility Mode 2.5 2.0 1.5 1.0 0.5 0 Frequency (MHz) 6 Fast Mode Frequency (MHz 3709D–MICRO–12/11 5.5V 5.0V 4.5V 3.6V 3.0V 2.4V 5.5V 5.0V 4.5V 3.6V 3.0V 2.4V ...

Page 97

... Quasi-Bidirectional Input Figure 18-5. Quasi-bidirectional Input Transition Current at 5V Figure 18-6. Quasi-bidirectional Input Transition Current at 3V 3709D–MICRO–12/11 0.0 0.5 1.0 1.5 2.0 2.5 0 -30 -60 -90 -120 -150 V IL 0.0 0.5 1.0 1.5 0 -10 -20 -30 -40 -50 -60 -70 - AT89LP51/52 3.0 3.5 4.0 4.5 5.0 (V) 2.0 2.5 3.0 (V) 85C -40C 25C 85C -40C 25C 97 ...

Page 98

... Quasi-Bidirectional Output Figure 18-7. Quasi-Bidirectional Output I-V Source Characteristic at 5V Figure 18-8. Quasi-Bidirectional Output I-V Source Characteristic at 3V AT89LP51/ -20 -40 -60 -80 -100 -120 -140 V OH 1.0 1.5 2.0 0 -10 -20 -30 -40 -50 -60 - (V) 2.5 3.0 (V) 85C -40C 25C 85C -40C 25C 3709D–MICRO–12/11 ...

Page 99

... Push-Pull Output Figure 18-9. Push-Pull Output I-V Source Characteristic at 5V Figure 18-10. Push-Pull Output I-V Source Characteristic at 3V 3709D–MICRO–12/ -10 V OH1 -10 V OH1 AT89LP51/ ( (V) 85C -40C 25C 85C -40C 25C 99 ...

Page 100

... Figure 18-11. Push-Pull Output I-V Sink Characteristic at 5V Figure 18-12. Push-Pull Output I-V Sink Characteristic at 3V Note: 18.4 Clock Characteristics The values shown in this table are valid for T Figure 18-13. External Clock Drive Waveform AT89LP51/52 100 0.0 0.1 0 0.0 0.2 0 The I /V characteristic applies to Push-Pull, Quasi-Bidirectional and Open-Drain modes. ...

Page 101

... Max Condition Low Power Oscillator High Power Oscillator T = 25° 5. 2 -40°C to 85°C and V = 2.4 to 5.5V, unless otherwise noted Condition AT89LP51/ 4.5V to 5.5V DD Min Max Units 0 25 MHz Min Max Units 0 ...

Page 102

... This assumes 50% clock duty cycle. The half period depends on the clock low value some cases parameter t 5. The strobe pulse width may be lengthened additional the internal system clock period. By default in Compatibility Mode, t CLCL AT89LP51/52 102 = -40°C to 85°C and and Figure 18-16 ...

Page 103

... LLWL t RLAZ t LLAX AVWL t AVDV A8 - A15 FROM DPH OR P2.0 - P2.7 t LHLL t t LLWL t QVWX t LLAX DATA OUT t QVWH t AVWL A8 - A15 FROM DPH OR P2.0 - P2.7 AT89LP51/52 t PLPH t LLIV PLIV t PXAV t PXIZ t PXIX INSTR A15 t WHLH t RLRH t t RLDV RHDZ t RHDX DATA IN t ...

Page 104

... Write to SBUF Output Data Clear RI Input Data Valid 18.8 Test Conditions 18.8.1 AC Testing Input/Output Waveform Note Inputs during testing are driven min. for a logic “1” and V IH AT89LP51/52 104 = 2.4V to 5.5V and Load Capacitance = 80 pF. DD SMOD1 = 0 Min 4t -15 CLCL 3t -15 CLCL t -15 ...

Page 105

... CLOCK SIGNAL GND RST POL GND (NC CLOCK SIGNAL GND Tests in Active and Idle Modes CHCL CHCX AT89LP51/52 ( CLCH CHCL t CHCX t CLCH t CLCL 105 ...

Page 106

... I Test Condition, Power-down Mode, All Other Pins are Disconnected AT89LP51/52 106 RST DD GND POL (NC) XTAL2 XTAL1 GND = 2V to 5.5V DD 3709D–MICRO–12/11 ...

Page 107

... Body, Plastic Very Thin Quad Flat No Lead Package (VQFN/MLF) 3709D–MICRO–12/11 Ordering Code AT89LP51-20AU AT89LP51-20PU 4KB AT89LP51-20JU AT89LP51-20MU AT89LP52-20AU AT89LP52-20PU 8KB AT89LP52-20JU AT89LP52-20MU Package Types AT89LP51/52 Package Operation Range 44A 40P6 Industrial 44J (-40° 85° C) 44M1 44A 40P6 Industrial 44J (-40° 85° C) ...

Page 108

... This package conforms to JEDEC reference MS-026, Variation ACB. 2. Dimensions D1 and E1 do not include mold protrusion. protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. 3. Lead coplanarity is 0.10 mm maximum. Package Drawing Contact: packagedrawings@atmel.com AT89LP51/52 108 ...

Page 109

... C E See Lead Detail Symbol 3. 0.356 0.204 D E 15.24 E1 12. TITLE 40P6, 40-lead, 0.600”/15.24 mm Wide Plastic Dual Inline Package (PDIP) AT89LP51/ -C- L COMMON DIMENSIONS (UNIT OF MEASURE=MM) Min. Nom. Max. Note - - 6.35 0. 4.95 - 0.558 0.77 - 1.77 - 0.381 50 ...

Page 110

... Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. 2325 Orchard Parkway San Jose, CA 95131 R AT89LP51/52 110 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER E1 E ...

Page 111

... Pin #1 Chamfer (C 0.30) Option C Pin #1 Notch e (0.20 R) TITLE 44M1, 44-pad 1.0 mm Body, Lead Pitch 0.50 mm, 5.20 mm Exposed Pad, Thermally Enhanced Plastic Very Thin Quad Flat No Lead Package (VQFN) AT89LP51/52 SEATING PLANE SIDE VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN MAX SYMBOL NOM A ...

Page 112

... Revision B – December 2010 Revision C – May 2011 Revision D – December 2011 AT89LP51/52 112 History • Initial Release • Added AT89LP51 device • Updated Device IDs • Lowered Minimum Operating Voltage to 2.4V • Added System Configuration (Section 2.2 on page • Added Code size to Ordering table • ...

Page 113

... System Configuration ........................................................................................7 2.3 Comparison to AT89S51/52 ..............................................................................8 3.1 Program Memory .............................................................................................11 3.2 Internal Data Memory ......................................................................................14 3.3 External Data Memory .....................................................................................14 3.4 In-Application Programming (IAP) ...................................................................23 5.1 Fast Mode ........................................................................................................25 5.2 Compatibility Mode ..........................................................................................26 5.3 Enhanced Dual Data Pointers .........................................................................26 6.1 Crystal Oscillator .............................................................................................29 6.2 External Clock Source .....................................................................................30 6.3 Internal RC Oscillator ......................................................................................30 6.4 System Clock Divider ......................................................................................31 7.1 Power-on Reset ...............................................................................................32 7.2 Brown-out Reset ..............................................................................................33 7.3 External Reset .................................................................................................33 7.4 Watchdog Reset ..............................................................................................34 AT89LP51/52 i ...

Page 114

... Table of Contents (Continued) 8 Power Saving Modes ............................................................................. 34 9 Interrupts ................................................................................................ 37 10 I/O Ports .................................................................................................. 41 11 Timer 0 and Timer 1 ............................................................................... 46 12 Timer 2 .................................................................................................... 51 13 External Interrupts ................................................................................. 57 14 Serial Interface (UART) .......................................................................... 57 AT89LP51/52 ii 7.5 Software Reset ................................................................................................34 8.1 Idle Mode .........................................................................................................34 8.2 Power-down Mode ...........................................................................................35 8.3 Reducing Power Consumption ........................................................................37 9.1 Interrupt Response Time .................................................................................38 10.1 Port Configuration ............................................................................................41 10.2 Port Read-Modify-Write ...................................................................................44 10.3 Port Alternate Functions ..................................................................................45 11.1 Mode 0 – ...

Page 115

... Clock Characteristics .....................................................................................100 18.5 Reset Characteristics ....................................................................................101 18.6 External Memory Characteristics ...................................................................102 18.7 Serial Port Timing: Shift Register Mode ........................................................104 18.8 Test Conditions ..............................................................................................104 19.1 Green Package Option (Pb/Halide-free) ........................................................107 20.1 44A – TQFP ...................................................................................................108 20.2 40P6 – PDIP ..................................................................................................109 20.3 44J – PLCC ...................................................................................................110 20.4 44M1 – VQFN/MLF .......................................................................................111 AT89LP51/52 iii ...

Page 116

... AT89LP51/52 iv 3709D–MICRO–12/11 ...

Page 117

... Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © 2011 Atmel Corporation. All rights reserved. Atmel marks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b ...