AT89LP51 Atmel Corporation, AT89LP51 Datasheet - Page 26

• Manufacturer Part Number: AT89LP51
• Manufacturer: Atmel Corporation

Specifications of AT89LP51

• Flash (kbytes): 4 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 36
• Uart: 1
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI
• Watchdog: Yes

5.2
5.3
26
Compatibility Mode
Enhanced Dual Data Pointers
AT89LP51/52
Compatibility (12-Clock) mode is enabled by default from the factory or by setting the Compati-
bility User Fuse. In Compatibility mode instruction bytes are fetched every three system clock
cycles and the CPU operates with 6-state machine cycles and a divide-by-2 system clock for 12
oscillator periods per machine cycle. Standard instructions execute in1, 2 or 4 machine cycles.
Instruction timing in this mode is compatible with standard 8051s such as the AT89S51/52.
Compatibility mode can be used to preserve the execution profiles of legacy applications. For a
summary of differences between Fast and Compatibility modes see
Examples of Compatibility mode instructions are shown in
Figure 5-2.
The AT89LP51/52 provides two 16-bit data pointers: DPTR0 formed by the register pair DPOL
and DPOH (82H an 83H), and DPTR1 formed by the register pair DP1L and DP1H (84H and
85H). The data pointers are used by several instructions to access the program or data memo-
ries. The Data Pointer Configuration Register (AUXR1) controls operation of the dual data
pointers
referenced by instructions including the DPTR operand. Each data pointer may be accessed at
its respective SFR addresses regardless of the DPS value. The AT89LP51/52 provides two
methods for fast context switching of the data pointers:
(A) 1-byte, 1-cycle instruction, e.g., INC A A
(B) 2-byte, 1-cycle instruction, e.g., ADD A, #data
(B) 2-byte, 1-cycle instruction, e.g., ADD A, #data
(C) 1-byte, 2-cycle instruction, e.g., INC DPTR
(C) 1-byte, 2-cycle instruction, e.g., INC DPTR
(D) MOVX (1-byte, 2-cycle)
(D) MOVX (1-byte, 2-cycle)
CLK
CLK
ALE
ALE
(Table 5-3 on page
Instruction Execution Sequences in Compatibility Mode
S1
S1
S1
S1
S1
S1
S1
S1
S1
S1
READ OPCODE
READ OPCODE
READ OPCODE
READ OPCODE
READ
READ
OPCODE
OPCODE
(MOVX)
(MOVX)
READ OPCODE
READ OPCODE
S2
S2
S2
S2
S2
S2
S2
S2
S2
S2
28). The DPS bit in AUXR1 selects which data pointer is currently
S3
S3
S3
S3
S3
S3
S3
S3
S3
S3
READ NEXT
READ NEXT
OPCODE (DISCARD)
OPCODE (DISCARD)
S4
S4
S4
S4
S4
S4
S4
S4
S4
S4
READ NEXT
READ NEXT
OPCODE
OPCODE
(DISCARD)
(DISCARD)
READ 2ND
READ 2ND
BYTE
BYTE
ACCESS EXTERNAL MEMOR
ACCESS EXTERNAL MEMORY
ADDR
ADDR
S5
S5
S5
S5
S5
S5
S5
S5
S5
S5
READ NEXT
READ NEXT
OPCODE (DISCARD)
OPCODE (DISCARD)
S6
S6
S6
S6
S6
S6
S6
S6
S6
S6
FETCH
FETCH
S1
S1
S1
S1
S1
S1
NO
NO
DA
DATA
READ NEXT OPCODE AGAIN
READ NEXT OPCODE AGAIN
READ NEXT OPCODE
READ NEXT OPCODE
S2
S2
S2
S2
S2
S2
Figure
NO
NO
ALE
ALE
S3
S3
S3
S3
S3
S3
5-2.
FETCH
FETCH
NO
NO
S4
S4
S4
S4
S4
S4
OPCODE AGAIN
OPCODE AGAIN
Table 2-3 on page
READ NEXT
READ NEXT
READ NEXT
READ NEXT
S5
S5
S5
S5
S5
S5
OPCODE
OPCODE
AGAIN
AGAIN
S6
S6
S6
S6
S6
S6
3709D–MICRO–12/11
S1
S1
10.