AT89LP51 Atmel Corporation, AT89LP51 Datasheet - Page 29

• Manufacturer Part Number: AT89LP51
• Manufacturer: Atmel Corporation

Specifications of AT89LP51

• Flash (kbytes): 4 Kbytes
• Max. Operating Frequency: 20 MHz
• Cpu: 8051-1C
• Max I/o Pins: 36
• Uart: 1
• Sram (kbytes): 0.25
• Eeprom (bytes): 256
• Self Program Memory: IAP
• Operating Voltage (vcc): 2.4 to 5.5
• Timers: 3
• Isp: SPI
• Watchdog: Yes

6. System Clock
6.1
3709D–MICRO–12/11
Crystal Oscillator
The system clock is generated directly from one of three selectable clock sources. The three
sources are the on-chip crystal oscillator, external clock source, and internal RC oscillator. A dia-
gram of the clock subsystem is shown in
configured for low or high power operation. The clock source is selected by the Clock Source
User Fuses as shown in
Fast mode no internal clock division is used to generate the CPU clock from the system clock. In
Compatibility mode the default is to divide the oscillator output by two. The system clock divider
may be used to prescale the system clock with other values. The choice of clock source also
affects the start-up time after a POR, BOD or Power-down event (See
“Power-down Mode” on page
Figure 6-1.
Table 6-1.
When enabled, the internal inverting oscillator amplifier is connected between XTAL1 and
XTAL2 for connection to an external quartz crystal or ceramic resonator. The oscillator may
operate in either high-power or low-power mode. Low-speed mode is intended for crystals of 12
MHz or less and consumes less power than the higher speed mode. The configuration as shown
in
capacitors C1 and C2 may NOT be required due to the on-chip capacitance of the XTAL1 and
XTAL2 inputs (approximately 10 pF each). When using the crystal oscillator, P4.6 and P4.7 will
have their inputs and outputs disabled. Also, XTAL2 in crystal oscillator mode should not be
used to directly drive a board-level clock without a buffer.
XTAL1
XTAL2
Figure 6-2
1.8432MHz
INTERNAL
Clock Source
OSC
Fuse 1
1
1
0
0
applies for both high and low power oscillators. Note that in some cases, external
Clock Subsystem Diagram
Clock Source Settings
Table
Clock Source
Fuse 0
35)
1
0
1
0
6-1. See
0
1
2
3
“User Configuration Fuses” on page
Figure
Selected Clock Source
High Power Crystal Oscillator (f > 12 MHz)
Low Power Crystal Oscillator (f ≤ 12 MHz)
External Clock on XTAL1
Internal 1.8432 MHz Auxiliary Oscillator
6-1. The on-chip crystal oscillator may also be
0
SYSTEM CLOCK
1 2 3 4 5
DIVIDER
(CLK
CLOCK
5-BIT
SYS
)
PRESCALER
AT89LP51/52
4-BIT
“Reset” on page 32
86. By default, in
Timer 0
Timer 1
Timer 2
Watchdog
29
or