AT89C5131A-L Atmel Corporation, AT89C5131A-L Datasheet - Page 37

• Manufacturer Part Number: AT89C5131A-L
• Manufacturer: Atmel Corporation

Specifications of AT89C5131A-L

• Flash (kbytes): 32 Kbytes
• Max. Operating Frequency: 48 MHz
• Cpu: 8051-12C
• Max I/o Pins: 34
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 1
• Twi (i2c): 1
• Uart: 1
• Sram (kbytes): 1.25
• Eeprom (bytes): 1024
• Self Program Memory: API
• Operating Voltage (vcc): 3.0 to 3.6
• Timers: 4
• Isp: UART/USB
• Watchdog: Yes

Flash Registers and
Memory Map
Hardware Registers
Bootloader Jump Bit (BLJB)
Flash Memory Lock Bits
4338F–USB–08/07
The AT89C5131A-L Flash memory uses several registers:
•
•
The only hardware register of the AT89C5131A-L is called Hardware Security Byte
(HSB).
Table 37. Hardware Security Byte (HSB)
One bit of the HSB, the BLJB bit, is used to force the boot address:
•
•
The three lock bits provide different levels of protection for the on-chip code and data,
when programmed as shown in Table 38.
Number
Bit
5-4
2-0
Hardware register can be accessed with a parallel programmer.Some bits of the
hardware register can be changed, also, by API (i.e. X2 and BLJB bits of Hardware
security Byte) or ISP.
Software registers are in a special page of the Flash memory which can be
accessed through the API or with the parallel programming modes. This page,
called “Extra Flash Memory”, is not in the internal Flash program memory
addressing space.
When this bit is set the boot address is 0000h.
When this bit is reset the boot address is F400h. By default, this bit is cleared and
the ISP is enabled.
X2
7
6
3
7
Mnemonic Description
OSCON1-0
LB2-0
BLJB
BLJB
Bit
X2
-
6
X2 Mode
Cleared to force X2 mode (6 clocks per instruction)
Set to force X1 mode, Standard Mode (Default).
Bootloader Jump Bit
Set this bit to start the user’s application on next reset at address 0000h.
Cleared this bit to start the bootloader at address F400h (default).
Oscillator Control Bits
These two bits are used to control the oscillator in order to reduce consumption.
OSCON1 OSCON0 Description
1
1
0
0
Reserved
User Memory Lock Bits
See Table 38
OSCON1
1 The oscillator is configured to run from 0 to 32 MHz
0 The oscillator is configured to run from 0 to 16 MHz
1 The oscillator is configured to run from 0 to 8 MHz
0 This configuration shouldn’t be set
5
OSCON0
4
3
-
LB2
2
LB1
1
LB0
0
37