T89C51CC02CA-TDSIM Atmel, T89C51CC02CA-TDSIM Datasheet

IC 8051 MCU FLASH 16K 24SOIC

T89C51CC02CA-TDSIM

Manufacturer Part Number
T89C51CC02CA-TDSIM
Description
IC 8051 MCU FLASH 16K 24SOIC
Manufacturer
Atmel
Series
AT89C CANr

Specifications of T89C51CC02CA-TDSIM

Core Processor
8051
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
20
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
24-SOIC (7.5mm Width)
For Use With
AT89STK-06 - KIT DEMOBOARD 8051 MCU W/CAN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
T89C51CC02CATDSIM

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
T89C51CC02CA-TDSIM
Manufacturer:
Microchip Technology
Quantity:
352
Features
Note:
80C51 Core Architecture
256 Bytes of On-chip RAM
256 Bytes of On-chip XRAM
16K Bytes of On-chip Flash Memory
Boot Code Section with Independent Lock Bits
2K Bytes of On-chip Flash for Bootloader
In-System Programming by On-Chip Boot Program (CAN, UART) and IAP Capability
2K Bytes of On-chip EEPROM
14-sources 4-level Interrupts
Three 16-bit Timers/Counters
Full Duplex UART Compatible 80C51
Maximum Crystal Frequency 40 MHz. In X2 Mode, 20 MHz (CPU Core, 40 MHz)
Three or Four Ports: 16 or 20 Digital I/O Lines
Two-channel 16-bit PCA
Double Data Pointer
21-bit Watchdog Timer (7 Programmable bits)
A 10-bit Resolution Analog-to-Digital Converter (ADC) with 8 Multiplexed Inputs
Full CAN Controller
1-Mbit/s Maximum Transfer Rate at 8 MHz
Readable Error Counters
Programmable Link to On-chip Timer for Time Stamping and Network Synchronization
Independent Baud Rate Prescaler
Data, Remote, Error and Overload Frame Handling
Power-saving Modes
Power Supply: 3 Volts to 5.5 Volts
Temperature Range: Industrial (-40° to +85°C)
Packages: SOIC28, SOIC24, PLCC28, VQFP32
– Data Retention: 10 Years at 85°C
– Erase/Write Cycle: 100K
– Erase/Write Cycle: 100K
– PWM (8-bit)
– High-speed Output
– Timer and Edge Capture
– Fully Compliant with CAN rev.# 2.0A and 2.0B
– Optimized Structure for Communication Management (Via SFR)
– 4 Independent Message Objects
– Supports
– Idle Mode
– Power-down Mode
-Each Message Object Programmable on Transmission or Reception
-Individual Tag and Mask Filters up to 29-bit Identifier/Channel
-8-byte Cyclic Data Register (FIFO)/Message Object
-16-bit Status and Control Register/Message Object
-16-bit Time-Stamping Register/Message Object
-CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message
Object
-Access to Message Object Control and Data Registers Via SFR
-Programmable Reception Buffer Length up to 4 Message Objects
-Priority Management of Reception of Hits on Several Message Objects
Simultaneously (Basic CAN Feature)
-Priority Management for Transmission
-Message Object Overrun Interrupt
-Time Triggered Communication
-Autobaud and Listening Mode
-Programmable Automatic Reply Mode
1. At BRP = 1 sampling point will be fixed.
(1)
Crystal Frequency In X2 Mode
Enhanced 8-bit
Microcontroller
with CAN
Controller and
Flash
T89C51CC02
AT89C51CC02
Rev. 4126L–CAN–01/08

Related parts for T89C51CC02CA-TDSIM

T89C51CC02CA-TDSIM Summary of contents

Page 1

Features • 80C51 Core Architecture • 256 Bytes of On-chip RAM • 256 Bytes of On-chip XRAM • 16K Bytes of On-chip Flash Memory – Data Retention: 10 Years at 85°C – Erase/Write Cycle: 100K • Boot Code Section with ...

Page 2

Description Block Diagram XTAL1 XTAL2 CPU AT/T89C51CC02 2 TM Part of the CANary family of 8-bit microcontrollers dedicated to CAN network applica- tions, the T89C51CC02 is a low-pin count 8-bit Flash microcontroller Mode a maximum external clock rate ...

Page 3

Pin Configurations 4126L–CAN–01/08 VAREF VAGND 26 VAVCC 3 25 P4.1/RxDC 4 P4.0/TxDC P2 P3.7 SO28 8 21 P3.6 P3.5/ P3.4/ P3.3/INT1 P3.2/INT0 17 ...

Page 4

AT/T89C51CC02 4 24 P4.0/TxDC P3.7 3 QFP- P3.5/ P3.4/ P3.3/INT1 8 P1.3/AN3/CEX0 P1.4/AN4/CEX1 P1.5/AN5 P1.6/AN6 P1.7/AN7 P2.0 NC RESET 4126L–CAN–01/08 ...

Page 5

Pin Description Pin Name Type Description VSS GND Circuit ground VCC Supply Voltage VAREF Reference Voltage for ADC (input) VAVCC Supply Voltage for ADC VAGND Reference Ground for ADC (internaly connected with the VSS) P1.0:7 I/O Port ...

Page 6

Pin Name Type Description P3.0:7 I/O Port 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s written to them are pulled high by the internal pull-up transistors and can be used as inputs ...

Page 7

I/O Configurations Port Structure 4126L–CAN–01/08 Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A CPU ’write to latch’ signal initiates transfer of internal bus data into the type-D latch. A CPU ...

Page 8

Read-Modify-Write Instructions Quasi Bi-directional Port Operation AT/T89C51CC02 8 Some instructions read the latch data rather than the pin data. The latch based instruc- tions read the data, modify the data and then rewrite the latch. These are called ’Read- Modify-Write’ ...

Page 9

This is traditional CMOS switch convention. Current strengths are 1/10 that of pFET #3. Note: During Reset, pFET#1 is not avtivated. During Reset, only the weak pFET#3 pull up the pin. Figure 2. Internal ...

Page 10

SFR Mapping Table 2. C51 Core SFRs Mnemonic Add Name ACC E0h Accumulator B F0h B Register PSW D0h Program Status Word SP 81h Stack Pointer Data Pointer Low byte DPL 82h LSB of DPTR Data Pointer High byte DPH ...

Page 11

Table 4. Timers SFRs (Continued) Mnemonic Add Name Timer/Counter 2 T2CON C8h control Timer/Counter 2 T2MOD C9h Mode Timer/Counter 2 RCAP2H CBh Reload/Capture High byte Timer/Counter 2 RCAP2L CAh Reload/Capture Low byte WatchDog Timer WDTRST A6h Reset WatchDog Timer WDTPRG ...

Page 12

Table 6. PCA SFRs (Continued) Mnemonic Add Name PCA Compare CCAP0L EAh Capture Module 0 L CCAP1L EBh PCA Compare Capture Module 1 L Table 7. Interrupt SFRs Mnemonic Add Name Interrupt Enable IEN0 A8h Control 0 Interrupt Enable IEN1 ...

Page 13

Table 9. CAN SFRs (Continued) Mnemonic Add Name CAN Enable CANEN CFh Channel byte CAN General CANGIE C1h Interrupt Enable CAN Interrupt CANIE C3h Enable Channel byte CAN Status Interrupt CANSIT BBh Channel byte CANTCON A1h CAN Timer Control CANTIMH ...

Page 14

Table 9. CAN SFRs (Continued) Mnemonic Add Name CAN Identifier Mask byte 2(PartA) CANIDM2 C5h CAN Identifier Mask byte 2(PartB) CAN Identifier Mask byte 3(PartA) CANIDM3 C6h CAN Identifier Mask byte 3(PartB) CAN Identifier Mask byte 4(PartA) CANIDM4 C7h CAN ...

Page 15

Table 11. SFR Mapping (1) 0/8 1/9 IPL1 CH F8h xxxx x000 0000 0000 B F0h 0000 0000 IEN1 CL E8h xxxx x000 0000 0000 ACC E0h 0000 0000 CCON CMOD D8h 0000 0000 0xxx x000 PSW FCON D0h 0000 ...

Page 16

Clock Description AT/T89C51CC02 16 The T89C51CC02 core needs only 6 clock periods per machine cycle. This feature, called “X2”, provides the following advantages: • Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power. • Saves power ...

Page 17

Figure 3. Clock CPU Generation Diagram Hardware Byte XTAL1 XTAL2 PD PCON.1 ÷ 2 ÷ CKCON.0 CANX2 CKCON.7 4126L–CAN–01/08 X2B PCON.0 On RESET IDL X2 CKCON.0 ÷ ÷ 2 ÷ ...

Page 18

Figure 4. Mode Switching Waveforms XTAL1 XTAL2 X2 bit CPU clock STD Mode Note order to prevent any incorrect operation while operating in the X2 Mode, users must be aware that all peripherals using the clock frequency as ...

Page 19

Register 4126L–CAN–01/08 Table 12. CKCON Register CKCON (S:8Fh) Clock Control Register CANX2 WDX2 PCAX2 Bit Bit Number Mnemonic Description (1) CAN Clock 7 CANX2 Clear to select 6 clock periods per peripheral clock cycle. Set to select ...

Page 20

Power Management Reset Pin At Power-up (cold reset) AT/T89C51CC02 20 Two power reduction modes are implemented in the A/T89C51CC02: the Idle mode and the Power-down mode. These modes are detailed in the following sections. In addition to these power reduction ...

Page 21

During a Normal Operation (Warm Reset) Watchdog Reset 4126L–CAN–01/08 Table 14. Minimum Reset Capacitor for a 15k Pull-down Resistor oscrst/vddrst 1ms 5ms 2.7µF 20ms 10µF Note: These values assume VDD starts from 0v to the nominal value. If the time ...

Page 22

Reset Recommendation to Prevent Flash Corruption Idle Mode Entering Idle Mode Exiting Idle Mode Power-down Mode Entering Power-down Mode AT/T89C51CC02 22 When a Flash program memory is embedded on-chip strongly recommended to use an external reset chip (brown ...

Page 23

Exiting Power-down Mode Figure 8. Power-down Exit Waveform Using INT1:0# INT1:0# OSC Active phase 4126L–CAN–01/08 V Note: If was reduced during the Power-down mode, do not exit Power-down mode until restored to the normal operating level. DD ...

Page 24

AT/T89C51CC02 24 Table 15. Pin Conditions in Special Operating Modes Down(inter Mode Port 1 Port 2 Port 3 Reset High High Idle (internal Data Data code) Idle (external Data Data code) Power- Data Data nal code) Power- Down Data Data ...

Page 25

Registers 4126L–CAN–01/08 Table 16. PCON Register PCON (S:87h) Power Control Register SMOD1 SMOD0 - Bit Bit Number Mnemonic Description Serial port Mode bit 1 7 SMOD1 Set to select double baud rate in mode ...

Page 26

Data Memory Internal Space Lower 128 Bytes RAM AT/T89C51CC02 26 The T89C51CC02 provides data memory access in two different spaces: The internal space mapped in three separate segments: • The lower 128 Bytes RAM segment. • The upper 128 Bytes ...

Page 27

Upper 128 Bytes RAM Expanded RAM 4126L–CAN–01/08 Figure 10. Lower 128 Bytes Internal RAM Organization 30h 20h 18h 10h 08h 00h The upper 128 Bytes of RAM are accessible from address 80h to FFh using only indirect addressing mode. The ...

Page 28

Dual Data Pointer Description Application AT/T89C51CC02 28 The T89C51CC02 implements a second data pointer for speeding up code execution and reducing code size in case of intensive usage of external memory accesses. DPTR0 and DPTR1 are Seen by the CPU ...

Page 29

Registers 4126L–CAN–01/08 Table 18. PSW Register PSW (S:D0h) Program Status Word Register Bit Bit Number Mnemonic Description Carry Flag 7 CY Carry out from bit 1 of ALU operands. Auxiliary Carry Flag 6 AC ...

Page 30

AT/T89C51CC02 30 Table 19. AUXR1 Register AUXR1 (S:A2h) Auxiliary Control Register ENBOOT Bit Bit Number Mnemonic Description Reserved The value read from these bits is indeterminate. Do not set these ...

Page 31

EEPROM Data Memory Write Data in the Column Latches Programming Read Data 4126L–CAN–01/08 The 2K bytes on-chip EEPROM memory block is located at addresses 0000h to 07FFh of the XRAM/XRAM memory space and is selected by setting control bits in ...

Page 32

Examples AT/T89C51CC02 32 ;*F************************************************************************* ;* NAME: api_rd_eeprom_byte ;* DPTR contain address to read. ;* Acc contain the reading value ;* NOTE: before execute this function, be sure the EEPROM is not BUSY ;*************************************************************************** api_rd_eeprom_byte: ; Save and clear EA MOV ...

Page 33

Registers 4126L–CAN–01/08 Table 20. EECON Register EECON (S:0D2h) EEPROM Control Register EEPL3 EEPL2 EEPL1 Bit Bit Number Mnemonic Description Programming Launch Command bits EEPL3-0 Write 5Xh followed by AXh to EEPL to launch the ...

Page 34

Program/Code Memory Flash Memory Architecture Figure 13. Flash Memory Architecture Hardware Security (1 byte) Extra Row (128 Bytes) Column Latches (128 Bytes) AT/T89C51CC02 34 The T89C51CC02 implement 16K Bytes of on-chip program/code memory. The Flash memory increases EPROM and ROM ...

Page 35

FM0 Memory Architecture User Space Extra Row (XRow) Hardware Security Byte Column Latches Cross Flash Memory Access Description 4126L–CAN–01/08 The Flash memory is made blocks (See Figure 13): 1. The memory array (user space) 16K Bytes 2. ...

Page 36

Overview of FM0 Operations Mapping of the Memory Space By default, the user space is accessed by MOVC instruction for read only. The column Launching Programming AT/T89C51CC02 36 The CPU interfaces the Flash memory through the FCON register and AUXR1 ...

Page 37

Status of the Flash Memory Selecting FM1 Loading the Column Latches 4126L–CAN–01/08 The bit FBUSY in FCON register is used to indicate the status of programming. FBUSY is set when programming is in progress. The bit ENBOOT in AUXR1 register ...

Page 38

Programming the Flash Spaces User Extra Row AT/T89C51CC02 38 Figure 14. Column Latches Loading Procedure Note: 1. The last page address used when loading the column latch is the one used to select the page programming address. The following procedure ...

Page 39

Hardware Security Byte 4126L–CAN–01/08 Figure 15. Flash and Extra row Programming Procedure The following procedure is used to program the Hardware and is summarized in Figure 16: • Set FPS and map Hardware byte (FCON = 0x0C) • Save then ...

Page 40

Reading the Flash Spaces User Extra Row Hardware Security Byte AT/T89C51CC02 40 Figure 16. Hardware Programming Procedure Flash Spaces Programming Save & Disable FCON = 0Ch Data Load DPTR = 00h ACC = Data Exec: MOVX ...

Page 41

Flash Protection from Parallel Programming Preventing Flash Corruption 4126L–CAN–01/08 Figure 17. Reading Procedure Note for the Hardware Security Byte. The three lock bits in Hardware Security Byte (See ’In-System Programming’ section) are programmed according to Table 24 ...

Page 42

Registers AT/T89C51CC02 42 Table 25. FCON Register FCON Register FCON (S:D1h) Flash Control Register FPL3 FPL2 FPL1 Bit Bit Number Mnemonic Description Programming Launch Command bits FPL3:0 Write 5Xh followed by AXh to launch ...

Page 43

AT/T89C51CC02 43 ...

Page 44

Operation Cross Memory Access Table 26. Cross Memory Access Action RAM Read boot FLASH Write Read FM0 Write Note: 1. RWW: Read While Write AT/T89C51CC02 44 Space addressable in read and write are: • RAM • ERAM (Expanded RAM access ...

Page 45

Sharing Instructions 4126L–CAN–01/08 Table 27. Instructions shared EEPROM Action RAM ERAM Read MOV MOVX Write MOV MOVX Note using Column Latch Table 28. Read MOVX A, @DPTR EEE bit in FPS in EECON Register FCON Register 0 ...

Page 46

Table 30. Read MOVC A, @DPTR FCON Register Code Execution FMOD1 FMOD0 From FM0 From FM1 (ENBOOT = For DPTR higher than 007Fh ...

Page 47

... There are three methods for programming the Flash memory: • The Atmel bootloader located in FM1 is activated by the application. Low level API routines (located in FM1)will be used to program FM0. The interface used for serial downloading to FM0 is the UART or the CAN. API can be called also by user’s bootloader located in FM0 at [SBV]00h. • ...

Page 48

... This bit indicates if on RESET the user wants to jump to this application at address @0000h on FM0 or execute the boot loader at address @F800h on FM1. - BLJB = 0 (i.e. bootloader FM1 executed after a reset) is the default Atmel factory pro- gramming. -To read or modify this bit, the APIs are used. ...

Page 49

XROW Bytes Hardware Conditions 4126L–CAN–01/08 The EXTRA ROW (XROW) includes 128 bytes. Some of these bytes are used for spe- cific purpose in conjonction with the bootloader. Table 31. XROW Mapping Description Copy of the Manufacturer Code Copy of the ...

Page 50

Hardware Security Byte AT/T89C51CC02 50 Table 32. Hardware Security byte X2B BLJB - Bit Bit Number Mnemonic Description X2 bit 7 X2B Set this bit to start in standard mode Clear this bit to start in X2 ...

Page 51

Serial I/O Port Figure 20. Serial I/O Port Block Diagram TXD RXD Framing Error Detection 4126L–CAN–01/08 The T89C51CC02 I/O serial port is compatible with the I/O serial port in the 80C52. It provides both synchronous and asynchronous communication modes. It ...

Page 52

Automatic Address Recognition Given Address AT/T89C51CC02 52 Figure 22. UART Timing in Mode 1 RXD D0 D1 Start bit RI SMOD0 = x FE SMOD0 = 1 Figure 23. UART Timing in Modes 2 and 3 RXD D0 D1 Start ...

Page 53

Broadcast Address 4126L–CAN–01/08 Here is an example of how to use given addresses to address different slaves: Slave A:SADDR1111 0001b SADEN1111 1010b Given1111 0X0Xb Slave B:SADDR1111 0011b SADEN1111 1001b Given1111 0XX1b Slave C:SADDR1111 0011b SADEN1111 1101b Given1111 00X1b The SADEN ...

Page 54

Registers AT/T89C51CC02 54 Table 33. SCON Register SCON (S:98h) Serial Control Register FE/SM0 SM1 SM2 Bit Bit Number Mnemonic Description Framing Error bit (SMOD0 = 1) FE Clear to reset the error state, not cleared by a ...

Page 55

Table 34. SADEN Register SADEN (S:B9h) Slave Address Mask Register Bit Bit Number Mnemonic Description Mask Data for Slave Individual Address Reset Value = 0000 0000b Not bit addressable Table 35. SADDR Register ...

Page 56

AT/T89C51CC02 56 Table 37. PCON Register PCON (S:87h) Power Control Register SMOD1 SMOD0 - Bit Bit Number Mnemonic Description Serial port Mode bit 1 7 SMOD1 Set to select double baud rate in mode ...

Page 57

Timers/Counters Timer/Counter Operations Timer 0 4126L–CAN–01/08 The T89C51CC02 implements two general-purpose, 16-bit Timers/Counters. Such are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer or an event ...

Page 58

Mode 0 (13-bit Timer) Figure 24. Timer/Counter x ( Mode 0 See section “Clock” FTx ÷ 6 CLOCK Tx C/Tx# TMOD Reg INTx# GATEx TMOD Reg Mode 1 (16-bit Timer) Figure 25. Timer/Counter x (x= 0 ...

Page 59

Figure 26. Timer/Counter x ( Mode 2 See section “Clock” FTx ÷ 6 CLOCK Tx C/Tx# TMOD Reg INTx# GATEx TMOD Reg Mode 3 (Two 8-bit Timers) Figure 27. Timer/Counter 0 in Mode 3: Two 8-bit ...

Page 60

Mode 0 (13-bit Timer) Mode 1 (16-bit Timer) Mode 2 (8-bit Timer with Auto- Reload) Mode 3 (Halt) Interrupt AT/T89C51CC02 60 • For normal Timer operation (GATE1= 0), setting TR1 allows TL1 to be incremented by the selected input. Setting ...

Page 61

Registers 4126L–CAN–01/08 Table 38. TCON Register TCON (S:88h) Timer/Counter Control Register TF1 TR1 TF0 Bit Bit Number Mnemonic Description Timer 1 Overflow Flag 7 TF1 Cleared by hardware when processor vectors to interrupt routine. Set by hardware ...

Page 62

AT/T89C51CC02 62 Table 39. TMOD Register TMOD (S:89h) Timer/Counter Mode Control Register GATE1 C/T1# M11 Bit Bit Number Mnemonic Description Timer 1 Gating Control bit 7 GATE1 Clear to enable Timer 1 whenever TR1 bit is set. ...

Page 63

Table 41. TL0 Register TL0 (S:8Ah) Timer 0 Low Byte Register Bit Bit Number Mnemonic Description 7:0 Low Byte of Timer 0 Reset Value = 0000 0000b Table 42. TH1 Register TH1 (S:8Dh) Timer 1 High ...

Page 64

Timer 2 Auto-Reload Mode Figure 29. Auto-Reload Mode Up/Down Counter See section “Clock” FT2 CLOCK T2 AT/T89C51CC02 64 The T89C51CC02 Timer 2 is compatible with Timer 2 in the 80C52 16-bit timer/counter: the count is maintained by ...

Page 65

Programmable Clock- Output Figure 30. Clock-Out Mode FT2 CLOCK T2 T2EX 4126L–CAN–01/08 In clock-out mode, Timer 2 operates as a 50%-duty-cycle, programmable clock genera- tor (Figure 30). The input clock increments TL2 at frequency f repeatedly counts to overflow from ...

Page 66

Registers AT/T89C51CC02 66 Table 44. T2CON Register T2CON (S:C8h) Timer 2 Control Register TF2 EXF2 RCLK Bit Bit Number Mnemonic Description Timer 2 Overflow Flag TF2 is not set if RCLK=1 or TCLK = 1. 7 TF2 ...

Page 67

Table 45. T2MOD Register T2MOD (S:C9h) Timer 2 Mode Control Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved ...

Page 68

AT/T89C51CC02 68 Table 47. TL2 Register TL2 (S:CCh) Timer 2 Low Byte Register Bit Bit Number Mnemonic Description Low Byte of Timer 2 Reset Value = 0000 0000b Not bit addressable ...

Page 69

Watchdog Timer Figure 31. Watchdog Timer RESET Fwd Clock WDTPRG - 4126L–CAN–01/08 T89C51CC02 contains a powerful programmable hardware Watchdog Timer (WDT) that automatically resets the chip if it software fails to reset the WDT before the selected time interval has ...

Page 70

Watchdog Programming AT/T89C51CC02 70 The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the WDT duration. Table 50. Machine Cycle Count ...

Page 71

Watchdog Timer During Power-down Mode and Idle Register 4126L–CAN–01/08 In Power-down mode the oscillator stops, which means the WDT also stops. While in Power-down mode, the user does not need to service the WDT. There are 2 methods of exiting ...

Page 72

AT/T89C51CC02 72 Table 53. WDTRST Register WDTRST (S:A6h Write Only) – Watchdog Timer Enable register Bit Bit Number Mnemonic Description 7 - Watchdog Control Value Reset Value = 1111 1111b Note: The WDRST register ...

Page 73

CAN Controller CAN Protocol Principles Message Formats Can Standard Frame Figure 32. CAN Standard Frames Data Frame Bus Idle 11-bit identifier SOF SOF Interframe Space Remote Frame Bus Idle 11-bit identifier SOF SOF Interframe Space 4126L–CAN–01/08 The CAN Controller provides ...

Page 74

CAN Extended Frame Figure 33. CAN Extended Frames Data Frame Bus Idle 11-bit base identifier SRR IDE SOF SOF IDT28..18 Interframe Arbitration Space Field Remote Frame Bus Idle 11-bit base identifier SRR IDE SOF SOF IDT28..18 Interframe Arbitration Space Field ...

Page 75

... It is the time required for the logic to determine the bit level of a sampled bit. The Information processing Time begins at the sample point, is measured in TQ and is fixed for the Atmel CAN. Since Phase Segment 2 also begins at the sample point and is the last segment in the bit time, Phase Segment 2 minimum shall not be less than the Information processing Time ...

Page 76

Bit Shortening Synchronization Jump Width Programming the Sample Point Arbitration Errors Error at Message Level AT/T89C51CC02 76 If, on the other hand, the transmitter oscillator is faster than the receiver one, the next falling edge used for resynchronization may be ...

Page 77

Error at Bit Level Error Signalling CAN Controller Description 4126L–CAN–01/08 fields against the fixed format and the frame size. Errors detected by frame checks are designated "format errors". • ACK Errors As already mentioned frames received are acknowledged by all ...

Page 78

Figure 36. CAN Controller Block Diagram TxDC RxDC CAN Controller Mailbox and Registers Organization AT/T89C51CC02 78 bit Error Timing Counter Logic Rec/Tec Page DPR(Mailbox + Registers) Register µC-Core Interface Interface Core Bus Control The pagination allows management of the 91 ...

Page 79

Figure 37. CAN Controller Memory Organization SFRs General Control General Status General Interrupt bit Timing - 1 bit Timing - 2 bit Timing - 3 Enable message object Enable Interrupt Enable Interrupt message object Status Interrupt message object Timer Control ...

Page 80

Working on Message Objects CAN Controller Management AT/T89C51CC02 80 The Page message object register (CANPAGE) is used to select one of the 4 message objects. Then, message object Control (CANCONCH) and message object Status (CANSTCH) are available for this selected ...

Page 81

Buffer Mode IT CAN Management 4126L–CAN–01/08 Any message object can be used to define one buffer, including non-consecutive mes- sage objects, and with no limitation in number of message objects used Each message object of the buffer ...

Page 82

Figure 39. CAN Controller Interrupt Structure CANGIE.5 ENRX RXOK i CANSTCH.5 TXOK i CANSTCH.6 BERR i CANSTCH.4 SERR i CANSTCH.3 CERR i CANSTCH.2 FERR i CANSTCH.1 AERR i CANSTCH.0 OVRBUF CANGIT.4 SERG CANGIT.3 CERG CANGIT.2 FERG CANGIT.1 AERG CANGIT.0 OVRTIM ...

Page 83

To enable an interrupt on Buffer-full condition: • Enable General CAN IT in the interrupt system register • Enable interrupt on Buffer full, ENBUF To enable an interrupt when Timer overruns: • Enable Overrun IT in the interrupt system ...

Page 84

Bit Timing and Baud Rate Figure 40. Sample and Transmission Point FCAN Prescaler BRP CLOCK AT/T89C51CC02 84 FSM’s (Finite State Machine) of the CAN channel need to be synchronous to the time quantum. So, the input clock for bit timing ...

Page 85

Figure 41. General Structure of a bit Period Oscillator System Clock Data (1) Phase error ≤ 0 (2) Phase error ≥ 0 (3) Phase error > 0 (4) Phase error < 0 4126L–CAN–01/08 1/ Fcan bit Rate Prescaler Tscl One ...

Page 86

Fault Confinement AT/T89C51CC02 86 With respect to fault confinement, a unit may be in one of the three following status: • Error active • Error passive • Bus off An error active unit takes part in bus communication and can ...

Page 87

Acceptance Filter 4126L–CAN–01/08 Upon a reception hit (i.e., a good comparison between the ID+RTR+RB+IDE received and an ID+RTR+RB+IDE specified while taking the comparison mask into account) the ID+RTR+RB+IDE received are written over the ID TAG Registers. ID => IDT0-29 RTR ...

Page 88

Data and Remote Frame message object in transmission message object disabled message object in transmission message object in reception by CAN controller message object disabled message object in transmission message object disabled message object in reception by user AT/T89C51CC02 88 ...

Page 89

Time Trigger Communication (TTC) and Message Stamping Figure 44. Block Diagram of CAN Timer Fcan ÷ 6 CLOCK TXOK i CANSTCH.4 RXOK i CANSTCH.5 CANSTMPH & CANSTMPL 4126L–CAN–01/08 The T89C51CC02 has a programmable 16-bit Timer (CANTIMH&CANTIML) for mes- sage stamp ...

Page 90

CAN Autobaud and Listening Mode Routine Examples AT/T89C51CC02 90 To activate the Autobaud feature, the AUTOBAUD bit in the CANGCON register must be set. In this mode, the CAN controller is only listening to the line without acknowledg- ing the ...

Page 91

Enable the CAN macro CANGCON = 02h 2. Configure message object 3 in reception to receive only standard (11bit identifier) message 100h // Select the message object 3 CANPAGE = 30h // Enable the interrupt on this message ...

Page 92

AT/T89C51CC02 92 // Find the first message object which generate an interrupt in CANSIT // Select the corresponding message object // Analyse the CANSTCH register to identify which kind of interrupt is generated // Manage the interrupt // Clear the ...

Page 93

CAN SFRs Table 55. SFR Mapping (1) 0/8 1/9 IPL1 CH F8h xxxx x000 0000 0000 B F0h 0000 0000 IEN1 CL E8h xxxx x000 0000 0000 ACC E0h 0000 0000 CCON CMOD D8h 0000 0000 0xxx x000 PSW FCON ...

Page 94

Registers AT/T89C51CC02 94 Table 56. CANGCON Register CANGCON (S:ABh) CAN General Control Register ABRQ OVRQ TTC SYNCTTC Bit Number Bit Mnemonic Description Abort Request Not an auto-resetable bit. A reset of the ENCH bit (message object control ...

Page 95

Table 57. CANGSTA Register CANGSTA (S:AAh Read Only) CAN General Status Register OVFG - Bit Number Bit Mnemonic Description Reserved 7 - The values read from this bit is indeterminate. Do not set this bit. ...

Page 96

AT/T89C51CC02 96 Table 58. CANGIT Register CANGIT (S:9Bh) CAN General Interrupt CANIT - OVRTIM Bit Number Bit Mnemonic Description General interrupt flag This status bit is the image of all the CAN controller interrupts sent 7 CANIT ...

Page 97

Table 59. CANTEC Register CANTEC (S:9Ch Read Only) – CAN Transmit Error Counter TEC7 TEC6 TEC5 Bit Number Bit Mnemonic Description Transmit Error Counter TEC7:0 See Figure 42 Reset Value = 00h Table ...

Page 98

AT/T89C51CC02 98 Table 61. CANGIE Register CANGIE (S:C1h) – CAN ENRX Bit Number Bit Mnemonic Description Reserved The values read from these bits are indeterminate. Do not set these bits. Enable ...

Page 99

Table 62. CANEN Register CANEN (S:CFh Read Only) CAN Enable Message Object Registers Bit Number Bit Mnemonic Description Reserved The values read from these bits are indeterminate. Do not ...

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AT/T89C51CC02 100 Table 64. CANIE Register CANIE (S:C3h) – CAN Enable Interrupt message object Registers Bit Number Bit Mnemonic Description Reserved The values read from these bits are indeterminate. Do ...

Page 101

Table 66. CANBT2 Register CANBT2 (S:B5h) – CAN bit Timing Registers SJW 1 SJW 0 Bit Number Bit Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set ...

Page 102

AT/T89C51CC02 102 Table 67. CANBT3 Register CANBT3 (S:B6h) CAN bit Timing Registers PHS2 2 PHS2 1 Bit Number Bit Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set ...

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Table 68. CANPAGE Register CANPAGE (S:B1h) – CAN Message Object Page Register CHNB 1 Bit Number Bit Mnemonic Description Reserved The values read from these bits are indeterminate. Do not ...

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AT/T89C51CC02 104 Table 70. CANSTCH Register CANSTCH (S:B2h) – CAN Message Object Status Register DLCW TXOK RXOK Bit Number Bit Mnemonic Description Data Length Code Warning The incoming message does not have the DLC expected. 7 DLCW ...

Page 105

Table 71. CANIDT1 Register for V2.0 part A CANIDT1 for V2.0 part A (S:BCh) – CAN Identifier Tag Registers IDT 10 IDT 9 IDT 8 Bit Number Bit Mnemonic Description IDentifier Tag Value 7 - ...

Page 106

AT/T89C51CC02 106 Table 74. CANIDT1 for V2.0 part A CANIDT4 for V2.0 part A (S:BFh) CAN Identifier Tag Registers Bit Number Bit Mnemonic Description Reserved The values read from ...

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Table 77. CANIDT3 Register for V2.0 Part B CANIDT3 for V2.0 Part B (S:BEh) CAN Identifier Tag Registers IDT 12 IDT 11 IDT 10 Bit Number Bit Mnemonic Description IDentifier Tag Value ...

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AT/T89C51CC02 108 Table 79. CANIDM1 Register for V2.0 part A CANIDM1 for V2.0 part A (S:C4h) CAN Identifier Mask Registers IDMSK 10 IDMSK 9 IDMSK 8 Bit Number Bit Mnemonic Description IDentifier Mask Value 0 - ...

Page 109

Table 82. CANIDM4 Register for V2.0 part A CANIDM4 for V2.0 part A (S:C7h) CAN Identifier Mask Registers Bit Number Bit Mnemonic Description Reserved The values read from ...

Page 110

AT/T89C51CC02 110 Table 84. CANIDM2 Register for V2.0 Part B CANIDM2 for V2.0 Part B (S:C5h) CAN Identifier Mask Registers IDMSK 20 IDMSK 19 IDMSK 18 IDMSK 17 Bit Number Bit Mnemonic Description IDentifier Mask Value ...

Page 111

Table 86. CANIDM4 Register for V2.0 Part B CANIDM4 for V2.0 Part B (S:C7h) CAN Identifier Mask Registers IDMSK 4 IDMSK 3 IDMSK 2 Bit Number Bit Mnemonic Description IDentifier Mask Value 0 - comparison ...

Page 112

AT/T89C51CC02 112 Table 88. CANTCON Register CANTCON (S:A1h) CAN Timer ClockControl TPRESC 7 TPRESC 6 TPRESC 5 TPRESC 4 Bit Number Bit Mnemonic Description Timer Prescaler of CAN Timer This register is a prescaler for the main ...

Page 113

Table 91. CANSTMPH Register CANSTMPH (S:AFh Read Only) CAN Stamp Timer High TIMSTMP TIMSTMP TIMSTMP Bit Number Bit Mnemonic Description High byte of Time Stamp TIMSTMP15:8 See Figure 44. No ...

Page 114

Programmable Counter Array (PCA) PCA Timer AT/T89C51CC02 114 The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its advantages include reduced software overhead and improved accu- racy. The PCA consists of a dedicated timer/counter which ...

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Figure 46. PCA Timer/Counter FPca/6 FPca/2 T0 OVF P1.2 Idle 4126L–CAN–01/08 CIDL CPS1 CPS0 CF CR The CMOD register includes three additional bits associated with the PCA. • The CIDL bit which allows the PCA to stop during idle mode. ...

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PCA Modules AT/T89C51CC02 116 Each one of the two compare/capture modules has six possible functions. It can perform: • 16-bit Capture, positive-edge triggered • 16-bit Capture, negative-edge triggered • 16-bit Capture, both positive and negative-edge triggered • 16-bit Software Timer ...

Page 117

PCA Interrupt Figure 47. PCA Interrupt System PCA Timer/Counter Module 0 Module 1 ECF CMOD.0 PCA Capture Mode Figure 48. PCA Capture Mode CEXn 4126L–CAN–01/ ECCFn CCAPMn.0 To use one of the PCA modules ...

Page 118

Software Timer Mode Figure 49. PCA 16-bit Software Timer and High Speed Output Mode PCA Counter CH (8 bits) (8 bits) “0” Reset Write to “1” CCAPnL Write to CCAPnH AT/T89C51CC02 118 The PCA modules can be used as ...

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High Speed Output Mode Figure 50. PCA High Speed Output Mode Write to CCAPnH Reset Write to CCAPnL “0” “1” Enable Pulse Width Modulator Mode 4126L–CAN–01/08 In this mode the CEX output (on port 1) associated with the PCA module ...

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Figure 51. PCA PWM Mode CL rolls over from FFh TO 00h loads CCAPnH contents into CCAPnL CL (8 bits) AT/T89C51CC02 120 CCAPnH CCAPnL “0” CL < CCAPnL 8-bit Comparator CL >= CCAPnL “1” ECOMn PWMn CCAPMn.6 CCAPMn.1 CEX 4126L–CAN–01/08 ...

Page 121

PCA Registers 4126L–CAN–01/08 Table 95. CMOD Register CMOD (S:D9h) PCA Counter Mode Register CIDL - - Bit Bit Number Mnemonic Description PCA Counter Idle Control bit 7 CIDL Clear to let the PCA run during Idle mode. ...

Page 122

AT/T89C51CC02 122 Table 96. CCON Register CCON (S:D8h) PCA Counter Control Register Bit Number Bit Mnemonic Description PCA Timer/Counter Overflow flag Set by hardware when the PCA Timer/Counter rolls over. This 7 CF generates ...

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Table 97. CCAPnH Registers CCAP0H (S:FAh) CCAP1H (S:FBh) PCA High Byte Compare/Capture Module n Register (n=0.. CCAPnH 7 CCAPnH 6 CCAPnH 5 Bit Number Bit Mnemonic Description 7:0 CCAPnH 7:0 High byte of EWC-PCA comparison or ...

Page 124

AT/T89C51CC02 124 Table 99. CCAPMn Registers CCAPM0 (S:DAh) CCAPM1 (S:DBh) PCA Compare/Capture Module n Mode registers (n=0.. ECOMn CAPPn Bit Number Bit Mnemonic Description Reserved 7 - The Value read from this bit is indeterminate. Do ...

Page 125

Table 100. CH Register CH (S:F9h) PCA Counter Register High value Bit Number Bit Mnemonic Description 7:0 CH 7:0 High byte of Timer/Counter Reset Value = 0000 00000b Table 101. ...

Page 126

Analog-to-Digital Converter (ADC) Features ADC Port1 I/O Functions VAREF AT/T89C51CC02 126 This section describes the on-chip 10-bit analog-to-digital converter of the T89C51CC02. Eight ADC channels are available for sampling of the external sources AN0 to AN7. An analog multiplexer allows ...

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Figure 52. ADC Description ADC CLOCK AN0/P1.0 000 AN1/P1.1 001 AN2/P1.2 010 AN3/P1.3 011 AN4/P1.4 100 AN5/P1.5 101 AN6/P1.6 110 AN7/P1.7 111 SCH2 SCH1 ADCON.2 ADCON.1 Figure 53. Timing Diagram CLK ADEN T SETUP ADSST ADEOC Note: Tsetup min, see ...

Page 128

Voltage Conversion Clock Selection Figure 54. A/D Converter Clock CPU CLOCK CPU Core Clock Symbol ADC Standby Mode AT/T89C51CC02 128 The bits SCH0 to SCH2 in ADCON register are used for the analog input channel selection. Table 102. Selected Analog ...

Page 129

IT ADC Management Routine Examples 4126L–CAN–01/08 An interrupt end-of-conversion will occurs when the bit ADEOC is activated and the bit EADC is set. For re-arming the interrupt the bit ADEOC must be cleared by software. Figure 55. ADC interrupt structure ...

Page 130

Registers AT/T89C51CC02 130 Table 103. ADCF Register ADCF (S:F6h) ADC Configuration Bit Bit Number Mnemonic Description Channel Configuration 0:7 Set to use P1.x as ADC input. Clear ...

Page 131

Table 105. ADCLK Register ADCLK (S:F2h) ADC Clock Prescaler Bit Bit Number Mnemonic Description Reserved The value read from these bits are indeterminate. Do not set these bits. Clock ...

Page 132

Interrupt System Introduction Figure 56. Interrupt Control System External INT0# Interrupt 0 Timer 0 External INT1# Interrupt 1 Timer 1 CEX0:1 PCA TxD UART RxD Timer 2 TxDC CAN Controller RxDC AIN1:0 Converter CAN Timer AT/T89C51CC02 132 ...

Page 133

Interrupt Name External interrupt (INT0) External interrupt (INT1) PCA (CF or CCFn) UART (RI or TI) CAN (Txok, Rxok, Err or OvrBuf) CAN Timer Overflow (OVRTIM) 4126L–CAN–01/08 Each of the interrupt sources can be individually enabled or disabled by setting ...

Page 134

Registers AT/T89C51CC02 134 Figure 57. IEN0 Register IEN0 (S:A8h) Interrupt Enable Register ET2 Bit Bit Number Mnemonic Description Enable All Interrupt bit Clear to disable all interrupts Set to enable all interrupts. If ...

Page 135

Figure 58. IEN1 Register IEN1 (S:E8h) Interrupt Enable Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved 6 - ...

Page 136

AT/T89C51CC02 136 Table 110. IPL0 Register IPL0 (S:B8h) Interrupt Enable Register PPC PT2 Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA Interrupt ...

Page 137

Table 111. IPL1 Register IPL1 (S:F8h) Interrupt Priority Low Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved ...

Page 138

AT/T89C51CC02 138 Table 112. IPH0 Register IPH0 (B7h) Interrupt High Priority Register PPCH PT2H Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. PCA ...

Page 139

Table 113. IPH1 Register IPH1 (S:F7h) Interrupt high priority Register Bit Bit Number Mnemonic Description Reserved 7 - The value read from this bit is indeterminate. Do not set this bit. Reserved ...

Page 140

Electrical Characteristics Absolute Maximum Ratings I = industrial ....................................................... -40°C to 85°C Storage Temperature ................................... -65° 150°C Voltage on V from V .....................................-0. Voltage on Any Pin from V .....................-0. ...

Page 141

Maximum I per 8-bit port: OL Ports 1, 2 and Maximum total I for all output pins exceeds the test condition than the listed test conditions. 4. Power-down I is ...

Page 142

DC Parameters for A/D Converter AT/T89C51CC02 142 Figure 61. I Test Condition, Power-down Mode VaVcc RST (NC) XTAL2 XTAL1 VAGND V SS Figure 62. Clock Signal Waveform for I V -0.5V CC 0.45V ...

Page 143

AC Parameters Serial Port Timing - Shift Register Mode 4126L–CAN–01/08 Table 116. Symbol Description ( MHz) Symbol T XLXL T QVHX T XHQX T XHDX T XHDV Table 117. AC Parameters for a Fix Clock ( ...

Page 144

Shift Register Timing Waveforms 0 INSTRUCTION CLOCK T QVXH OUTPUT DATA WRITE to SBUF INPUT DATA CLEAR RI External Clock Drive Characteristics (XTAL1) External Clock Drive Waveforms AC Testing Input/Output Waveforms Float Waveforms AT/T89C51CC02 144 ...

Page 145

Clock Waveforms Flash/EEPROM Memory A/D Converter 4126L–CAN–01/08 For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins to float when a 100 mV change from the loaded V ≥ ...

Page 146

... Ordering Information Part Number T89C51CC02CA-RATIM T89C51CC02CA-SISIM T89C51CC02CA-TDSIM T89C51CC02CA-TISIM T89C51CC02UA-RATIM T89C51CC02UA-SISIM T89C51CC02UA-TDSIM T89C51CC02UA-TISIM AT89C51CC02CA-RATUM AT89C51CC02CA-SISUM AT89C51CC02CA-TDSUM AT89C51CC02CA-TISUM AT89C51CC02UA-RATUM AT89C51CC02UA-SISUM AT89C51CC02UA-TDSUM AT89C51CC02UA-TISUM AT/T89C51CC02 146 Temperature Bootloader Range (2) CAN Industrial & Green (2) CAN Industrial & Green (2) CAN Industrial & Green (2) CAN Industrial & Green ...

Page 147

Package Drawings VQFP32 4126L–CAN–01/08 AT/T89C51CC02 147 ...

Page 148

STANDARD NOTES FOR PQFP/ VQFP / TQFP / DQFP 1/ CONTROLLING DIMENSIONS : INCHES 2/ ALL DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y 14.5M - 1982. 3/ "D1 AND E1" DIMENSIONS DO NOT INCLUDE MOLD PROTUSIONS. MOLD PROTUSIONS SHALL NOT ...

Page 149

PLCC28 4126L–CAN–01/08 AT/T89C51CC02 149 ...

Page 150

STANDARD NOTES FOR PLCC 1/ CONTROLLING DIMENSIONS : INCHES 2/ DIMENSIONING AND TOLERANCING PER ANSI Y 14.5M - 1982. 3/ "D" AND "E1" DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTUSIONS. MOLD FLASH OR PROTUSIONS SHALL NOT EXCEED 0.20 mm ...

Page 151

SOIC24 4126L–CAN–01/08 AT/T89C51CC02 151 ...

Page 152

SOIC28 AT/T89C51CC02 152 4126L–CAN–01/08 ...

Page 153

AT/T89C51CC02 153 ...

Page 154

Datasheet Revision History Changes from 4126C- 10/02 to 4126D - 04/03 Changes from 4126D - 05/03 to 4126E - 10/03 Changes from 4126E - 10/03 to 4126F - 12/03 Changes from 4126F - 12/03 4126G - 08/04 Changes from 4126G ...

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Table of Features ................................................................................................. 1 Contents Description ............................................................................................ 2 Block Diagram ....................................................................................... 2 Pin Configurations ................................................................................ 3 Pin Description...................................................................................... 5 SFR Mapping ....................................................................................... 10 Clock .................................................................................................... 16 Power Management ............................................................................ 20 Reset Pin .............................................................................................. 20 Data Memory ....................................................................................... 26 EEPROM ...

Page 156

Program/Code Memory ...................................................................... 34 Operation Cross Memory Access ..................................................... 44 Sharing Instructions ........................................................................... 45 In-System Programming (ISP) ........................................................... 47 Serial I/O Port ...................................................................................... 51 Timers/Counters ................................................................................. 57 Timer 2 ................................................................................................. 64 Watchdog Timer .................................................................................. 69 Watchdog Timer During Power-down Mode ...

Page 157

CAN Protocol...................................................................................................... 73 CAN Controller Description ................................................................................ 77 CAN Controller Mailbox and Registers Organization ......................................... 78 CAN Controller Management ............................................................. 80 IT CAN Management.......................................................................................... 81 Bit Timing and Baud Rate .................................................................................. 84 Fault Confinement .............................................................................................. 86 Acceptance Filter................................................................................................ 87 Data ...

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Ordering Information ........................................................................ 146 Package Drawings ............................................................................ 147 Datasheet Revision History ............................................................. 154 Table of Contents ................................................................................... i iv Absolute Maximum Ratings.............................................................................. 140 DC Parameters for Standard Voltage............................................................... 140 DC Parameters for A/D Converter.................................................................... 142 AC Parameters ................................................................................................. 143 VQFP32............................................................................................................ ...

Page 159

... Atmel does not make any commitment to update the information contained herein. Unless specifically providedot- herwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as compo- nents in applications intended to support or sustain life. © ...

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