AT32UC3L0128 Atmel Corporation, AT32UC3L0128 Datasheet - Page 379
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AT32UC3L0128
Manufacturer Part Number
AT32UC3L0128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3L0128.pdf
(85 pages)
4.AT32UC3L0128.pdf
(852 pages)
Specifications of AT32UC3L0128
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
4
Lin
4
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
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19.6
19.6.1
Figure 19-2. Baud Rate Generator
19.6.1.1
19.6.1.2
32145A–12/2011
Functional Description
Baud Rate Generator
CLK_USART/DIV
CLK
CLK_USART
Baud Rate in Asynchronous Mode
Baud Rate Calculation Example
Reserved
USCLKS
The baud rate generator provides the bit period clock named the Baud Rate Clock to both
receiver and transmitter. It is based on a 16-bit divider, which is specified in the Clock Divider
field in the Baud Rate Generator Register (BRGR.CD). A non-zero value enables the generator,
and if CD is one, the divider is bypassed and inactive. The Clock Selection field in the Mode
Register (MR.USCLKS) selects clock source between:
If the external CLK clock is selected, the duration of the low and high levels of the signal pro-
vided on the CLK pin must be at least 4.5 times longer than those provided by CLK_USART.
If the USART is configured to operate in an asynchronous mode, the selected clock is divided by
the CD value before it is provided to the receiver as a sampling clock. Depending on the Over-
sampling Mode bit (MR.OVER) value, the clock is then divided by either 8 (OVER=1), or 16
(OVER=0). The baud rate is calculated with the following formula:
This gives a maximum baud rate of CLK_USART divided by 8, assuming that CLK_USART is
the fastest clock possible, and that OVER is one.
Table 19-3
clock frequencies. This table also shows the actual resulting baud rate and error.
0
1
3
2
• CLK_USART (internal clock)
• CLK_USART/DIV (a divided CLK_USART, refer to Module Configuration section)
• CLK (external clock, available on the CLK pin)
BaudRate
shows calculations based on the CD field to obtain 38400 baud from different source
16-bit Counter
=
CD
----------------------------------------------- -
8 2 OVER
SelectedClock
–
USCLKS= 3
0
SYNC
CD
CD
>1
0
1
0
1
OVER
Sampling
Divider
AT32UC3L0128/256
FIDI
0
1
SYNC
CLK
BaudRate
Sampling
Clock
Clock
379
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