AT32UC3L0128 Atmel Corporation, AT32UC3L0128 Datasheet - Page 537
AT32UC3L0128
Manufacturer Part Number
AT32UC3L0128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3L0128.pdf
(85 pages)
4.AT32UC3L0128.pdf
(852 pages)
Specifications of AT32UC3L0128
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
4
Lin
4
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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23.6.4
23.6.5
23.6.6
23.6.6.1
32145A–12/2011
Duty Cycle and Waveform Properties
Waveform Output
Updating Duty Cycle Values
Interlinked Single Value PWM Operation
When writing a one to CR.TCLR, the timebase counter and the spread spectrum counter are
reset at their lower limit values and the effective top value of the timebase counter will also be
reset.
Each PWM channel has its own duty cycle value (DCV) which is write-only and cannot be read
out. The duty cycle value can be changed in two approaches as described in Section23.6.6.
When the duty cycle value is zero, the PWM output is zero. Otherwise, the PWM output is set
when the timebase counter is zero, and cleared when the timebase counter reaches the duty
cycle value. This is summarized as:
Note that when increasing the duty cycle value for one channel from 0 to 1, the number of GCLK
cycles when the PWM waveform is high will jump from 0 to 2. When incrementing the duty cycle
value by one for any other values, the number of GCLK cycle when the waveform is high will
increase by one. This is summarized in
Table 23-2.
PWMA waveforms are output to I/O lines. The output waveform properties are controlled by
Composite Waveform Generation (CWG) register(s). If this register is cleared (by default), the
channel waveforms are out directly to the I/O lines. To avoid too many I/O toggling simultane-
ously on the output I/O lines, every other output PWM waveform toggles on the negative edge of
the GCLK instead of the positive edge.
In CWG mode, all channels are paired and their outputs are XOR’ed together if the correspond-
ing bit of CWG register is set. The even number of output is the XOR’ed output and the odd
number of output is the inverse of its. Each bit of CWG register controls one pair channels and
the least significant bit refers to the lowest number of pair channels.
The PWM channels can be interlinked to allow multiple channels to be updated simultaneously
with the same duty cycle value. This value must be written to the Interlinked Single Value Duty
Duty Cycle Value
0
1
2
...
ETV-1
ETV
PMW Waveform Duty Cycles
PWM Waveform =
#Clock Cycles
When Waveform is High
0
2
3
...
ETV
ETV+1
⎧
⎨
⎩
Table
high when TC DCV and DCV 0
low when DCV
23-2.
=
0 or TC DCV
AT32UC3L0128/256
#Clock Cycles
When Waveform is Low
ETV+1
ETV-1
ETV-2
...
1
0
537
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