AT32UC3L0128 Atmel Corporation, AT32UC3L0128 Datasheet - Page 169
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AT32UC3L0128
Manufacturer Part Number
AT32UC3L0128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(159 pages)
3.AT32UC3L0128.pdf
(85 pages)
4.AT32UC3L0128.pdf
(852 pages)
Specifications of AT32UC3L0128
Flash (kbytes)
128 Kbytes
Pin Count
48
Max. Operating Frequency
50 MHz
Cpu
32-bit AVR
# Of Touch Channels
17
Hardware Qtouch Acquisition
Yes
Max I/o Pins
36
Ext Interrupts
36
Usb Speed
No
Usb Interface
No
Spi
5
Twi (i2c)
2
Uart
4
Lin
4
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
12
Adc Speed (ksps)
460
Analog Comparators
8
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
16
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.62 to 3.6
Operating Voltage (vcc)
1.62 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
18
Input Capture Channels
12
Pwm Channels
35
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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12.7.6
Name:
Access Type:
Offset:
Reset Value:
• MASK: Clock Mask
Table 12-10. Divided Clock Mask
Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please
refer to the UNLOCK register description for details.
32145A–12/2011
Bit
0
1
2
3
4
5
6
31
23
15
7
-
-
-
-
If bit n is written to zero, the clock divided by 2
according to the current power mode.
CLK_USART/
USART0
PBA Divided Mask
DIV
-
-
-
-
-
-
30
22
14
6
-
-
PBADIVMASK
Read/Write
0x040
0x0000007F
CLK_USART/
USART1
DIV
-
-
-
-
-
-
29
21
13
5
-
-
-
CLK_USART/
Table 12-10
USART2
DIV
-
-
-
-
-
-
(n+1)
28
20
12
4
-
-
-
is stopped. If bit n is written to one, the clock divided by 2
shows what clocks are affected by the different MASK bits.
CLK_USART/
USART3
DIV
MASK[6:0]
-
-
-
-
-
-
27
19
11
3
-
-
-
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
26
18
10
2
-
-
-
TC0
-
-
-
AT32UC3L0128/256
25
17
9
1
-
-
-
TIMER_CLOCK2
TIMER_CLOCK3
TIMER_CLOCK4
TIMER_CLOCK5
(n+1)
TC1
is enabled
-
-
-
24
16
8
0
-
-
-
169
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