AT32UC3A4128 Atmel Corporation, AT32UC3A4128 Datasheet - Page 92
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AT32UC3A4128
Manufacturer Part Number
AT32UC3A4128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4128
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 92 of 377
- Download datasheet (5Mb)
8.4
8.5
92
Event priority
Event handling in secure state
AVR32
Several instructions may be in the pipeline at the same time, and several events may be issued
in each pipeline stage. This implies that several pending exceptions may be in the pipeline
simultaneously. Priorities must therefore be imposed, ensuring that the correct event is serviced
first. The priority scheme obeys the following rules:
Details about the timing of events is IMPLEMENTATION DEFINED, and given in the hardware
manual for the specific implementation.
Interrupt and exception handling in AVR32A and AVR32B has been described in the previous
chapters. This behavior is modified in the following way when interrupts and exceptions are
received in secure state:
Note that in the secure state, all exception sources share the same handler address. It is there-
fore not possible to separate different exception causes when in the secure world. The secure
world system must be designed to support this, the most obvious solution is to design the secure
software so that exceptions will not arise.
1. If several instructions trigger events, the instruction furthest down the pipeline is ser-
2. If this instruction has several pending events, the event with the highest priority is ser-
• A sscall instruction will set SR[GM]. In secure state, SR[GM] masks both INT0-INT3, and
• sscall has handler address at offset 0x4 relative to the reset handler address.
• Exceptions have a handler address at offset 0x8 relative to the reset handler address.
• NMI has a handler address at offset 0xC relative to the reset handler address.
• BREAKPOINT has a handler address at offset 0x10 relative to the reset handler address.
• INT0-INT3 are not autovectored, but have a common handler address at offset 0x14 relative
NMI. Clearing SR[GM], INT0-INT3 and NMI will remove the mask of these event sources.
INT0-INT3 are still additionally masked by the I0M-I3M bits in the status register.
to the reset handler address.
viced first, even if upstream instructions have pending events of higher priority.
viced first. After this event has been serviced, all pending events are cleared and the
instruction is restarted.
32000D–04/2011
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