AT32UC3A4128 Atmel Corporation, AT32UC3A4128 Datasheet - Page 40
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AT32UC3A4128
Manufacturer Part Number
AT32UC3A4128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4128
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 40 of 377
- Download datasheet (5Mb)
5.2.2.3
5.2.2.4
5.2.2.5
40
AVR32
Page Table Base Register - PTBR
TLB Exception Address Register - TLBEAR
MMU Control Register - MMUCR
Table 5-2.
Table 5-3.
This register points to the start of the page table structure. The register is not used by hardware,
and can only be modified by software. The register is meant to be used by the MMU-related
exception routines.
This register contains the virtual address that caused the most recent MMU-related exception.
The register is updated by hardware when such an exception occurs.
The MMUCR controls the operation of the MMU. The MMUCR has the following fields:
AP
000
001
010
011
100
101
110
111
SZ
00
01
10
11
• SZ - Size of the page. The following page sizes are provided, see
• D - Dirty bit. Set if the page has been written to, cleared otherwise. If the memory access is a
• W - Write through. If set, a write-through cache update policy should be used. Write-back
• IRP - Instruction TLB Replacement Pointer. Points to the ITLB entry to overwrite when a new
store and the D bit is cleared, an Initial Page Write exception is raised.
should be used otherwise. The bit is ignored if the cache only supports write-through or write-
back.
entry is loaded by the tlbw instruction. The IRP field may be updated automatically in an
IMPLEMENTATION DEFINED manner in order to optimize the replacement algorithm. The
IRP field can also be written by software, allowing the exception routine to implement a
replacement algorithm in software. The IRP field is 6 bits wide, allowing a maximum of 64
Access permissions implied by the AP bits
Page sizes implied by the SZ bits
Privileged mode
Read
Read / Execute
Read / Write
Read / Write / Execute
Read
Read / Execute
Read / Write
Read / Write / Execute
Page size
1 kB
4 kB
64 kB
1 MB
Bits used in VPN
TLBEHI[31:10]
TLBEHI[31:12]
TLBEHI[31:16]
TLBEHI[31:20]
Bits used in PFN
TLBELO[31:10]
TLBELO[31:12]
TLBELO[31:16]
TLBELO[31:20]
Unprivileged mode
None
None
None
None
Read
Read / Execute
Read / Write
Read / Write / Execute
Table
5-3:
32000D–04/2011
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