AT32UC3A4128 Atmel Corporation, AT32UC3A4128 Datasheet - Page 11
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AT32UC3A4128
Manufacturer Part Number
AT32UC3A4128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4128
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 11 of 377
- Download datasheet (5Mb)
2.8
2.9
2.10
32000D–04/2011
The Program Counter
The Link Register
The Status Register
The Program Counter (PC) contains the address of the instruction being executed. The memory
space is byte addressed. With the exception of Java state, the instruction size is a multiple of 2
bytes and the LSB of the Program Counter is fixed to zero. The PC is automatically incremented
in normal program flow, depending on the size of the current instruction.
The PC is mapped into the register file and it can be used as a source or destination operand in
all instructions using register operands. This includes arithmetical or logical instructions and
load/store instructions. Instructions using PC as destination register are treated the same way
as jump instructions. This implies that the pipeline is flushed, and execution resumed at the
address specified by the new PC value.
The general purpose register R14 is used as a Link Register in all modes. The Link Register
holds subroutine return addresses. When a subroutine call is performed by a variant of the call
instruction, LR is set to hold the subroutine return address. The subroutine return is performed
by copying LR back to the program counter, either explicitly by a mov instruction, by using a ldm
or popm instruction or a ret instruction.
The Link Register R14 can be used as a general-purpose register at all other times.
The Status Register (SR) is split into two halfwords, one upper and one lower, see
page 11
while the upper halfword contains information about the mode and state the processor executes
in. The upper halfword can only be accessed from a privileged mode.
Figure 2-6.
B it 3 1
S S
0
L C
1
0
-
and
H
0
Figure 2-7 on page
The Status Register high halfword
J
0
D M
0
D
0
0
-
M 2
0
12. The lower halfword contains the C, Z, N, V and Q flags,
M 1
0
M 0
1
E M
1
I3 M
0
I2 M
F E
0
I1 M
0
I0 M
0
B it 1 6
G M
1
B it n a m e
In itia l v a lu e
G lo b a l In te rru p t M a s k
In te r ru p t L e v e l 0 M a s k
In te r ru p t L e v e l 1 M a s k
In te r ru p t L e v e l 2 M a s k
In te r ru p t L e v e l 3 M a s k
E x c e p tio n M a s k
M o d e B it 0
M o d e B it 1
M o d e B it 2
R e s e rv e d
D e b u g S ta te
D e b u g S ta te M a s k
J a v a S ta te
J a v a H a n d le
R e s e rv e d
S e c u re S ta te
Figure 2-6 on
AVR32
11
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