AT32UC3A4128 Atmel Corporation, AT32UC3A4128 Datasheet - Page 19
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AT32UC3A4128
Manufacturer Part Number
AT32UC3A4128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4128
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 19 of 377
- Download datasheet (5Mb)
32000D–04/2011
JAVA_LVx - Java Local Variable Registers
JTBA - Java Trap Base Address
JBCR - Java Write Barrier Control Register
CONFIG0 / 1 - Configuration Register 0 / 1
COUNT - Cycle Counter Register
COMPARE - Cycle Counter Compare Register
TLBEHI - MMU TLB Entry Register High Part
TLBELO - MMU TLB Entry Register Low Part
PTBR - MMU Page Table Base Register
TLBEAR - MMU TLB Exception Address Register
The Java Extension Module uses these registers to store local variables temporary.
This register contains the base address to the program code for the trapped Java instructions.
This register is used by the garbage collector in the Java Virtual Machine.
Used to describe the processor, its configuration and capabilities. The contents and functionality
of these registers is described in detail in
The COUNT register increments once every clock cycle, regardless of pipeline stalls and
flushes. The COUNT register can both be read and written. The count register can be used
together with the COMPARE register to create a timer with interrupt functionality. The COUNT
register is written to zero upon reset and compare match. Revision 3 of the AVR32 Architecture
allows some implementations to disable this automatic clearing of COUNT upon COMPARE
match, usually by programming a bit in CPUCR. Refer to the Technical Reference Manual for
the device for details. Incrementation of the COUNT register can not be disabled. The COUNT
register will increment even though a compare interrupt is pending.
The COMPARE register holds a value that the COUNT register is compared against. The COM-
PARE register can both be read and written. When the COMPARE and COUNT registers match,
a compare interrupt request is generated and COUNT is reset to 0. This interrupt request is
routed out to the interrupt controller, which may forward the request back to the processor as a
normal interrupt request at a priority level determined by the interrupt controller. Writing a value
to the COMPARE register clears any pending compare interrupt requests. The compare and
exception generation feature is disabled if the COMPARE register contains the value zero. The
COMPARE register is written to zero upon reset.
Used to interface the CPU to the TLB. The contents and functionality of the register is described
in detail in
Used to interface the CPU to the TLB. The contents and functionality of the register is described
in detail in
Contains a pointer to the start of the Page Table. The contents and functionality of the register is
described in detail in
Contains the virtual address that caused the most recent MMU error. The contents and function-
ality of the register is described in detail in
Section 5. “Memory Management Unit” on page
Section 5. “Memory Management Unit” on page
Section 5. “Memory Management Unit” on page
Section 2.11.1 “Configuration Registers” on page
Section 5. “Memory Management Unit” on page
35.
35.
35.
AVR32
35.
21.
19
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