AT32UC3A4128 Atmel Corporation, AT32UC3A4128 Datasheet - Page 111
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AT32UC3A4128
Manufacturer Part Number
AT32UC3A4128
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(377 pages)
2.AT32UC3A0128.pdf
(33 pages)
3.AT32UC3A0128.pdf
(159 pages)
4.AT32UC3A3128.pdf
(91 pages)
5.AT32UC3A3128.pdf
(1012 pages)
Specifications of AT32UC3A4128
Flash (kbytes)
128 Kbytes
Pin Count
100
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
Hardware Qtouch Acquisition
No
Usb Transceiver
1
Usb Speed
Hi-Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
2
Uart
4
Sd / Emmc
2
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
128
Self Program Memory
YES
Dram Memory
No
Nand Interface
Yes
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0 to 3.6
Operating Voltage (vcc)
3.0 to 3.6
Fpu
No
Mpu / Mmu
Yes / No
Timers
6
Output Compare Channels
6
Input Capture Channels
6
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
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- AT32UC3A0128 PDF datasheet
- AT32UC3A0128 PDF datasheet #2
- AT32UC3A0128 PDF datasheet #3
- AT32UC3A3128 PDF datasheet #4
- AT32UC3A3128 PDF datasheet #5
- Current page: 111 of 377
- Download datasheet (5Mb)
9.3.6
Table 9-6.
32000D–04/2011
Mnemonics
bfexts
bfextu
bfins
bld
brev
bst
casts.b
casts.h
castu.b
castu.h
cbr
clz
sbr
swap.b
swap.bh
swap.h
Bit Operations
Bit Operations
E
E
E
E
C
E
C
C
C
C
C
E
C
C
C
C
Operands / Syntax
Rd, Rs, o5, w5
Rd, Rs, o5, w5
Rd, Rs, o5, w5
Rd, bp
Rd
Rd, bp
Rd
Rd
Rd
Rd
Rd, bp
Rd, Rs
Rd, bp
Rd
Rd
Rd
Description
Extract and sign-extend the w5 bits in Rs
starting at bit-offset o5 to Rd.
Extract and zero-extend the w5 bits in Rs
starting at bit-offset o5 to Rd.
Insert the lower w5 bits of Rs in Rd at bit-
offset o5.
Bit load.
Bit reverse.
Bit store.
Typecast byte to signed word.
Typecast halfword to signed word.
Typecast byte to unsigned word.
Typecast halfword to unsigned word.
Clear bit in register.
Count leading zeros.
Set bit in register.
Swap bytes in register.
Swap bytes in each halfword.
Swap halfwords in register.
Rd ← SE(Rd[15:0])
Rd ← ZE(Rd[7:0])
Rd ← ZE(Rd[15:0])
Rd[bp5] ← 0
Operation
See Instruction Set Reference
See Instruction Set Reference
See Instruction Set Reference
C ← Rd[bp5]
Z ← Rd[bp5]
Rd[0:31] ← Rd[31:0]
Rd[bp5] ← C
Rd ← SE(Rd[7:0])
See Instruction Set Reference
Rd[bp5] ← 1
Rd[31:24] ← Rd[7:0],
Rd[23:16] ← Rd[15:8],
Rd[15:8] ← Rd[23:16],
Rd[7:0] ← Rd[31:24]
Rd[31:24] ← Rd[23:16],
Rd[23:16] ← Rd[31:24],
Rd[15:8] ← Rd[7:0],
Rd[7:0] ← Rd[15:8]
Rd[31:16] ← Rd[15:0],
Rd[15:0] ← Rd[31:16]
AVR32
Rev
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
111
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