AT32UC3A364S Atmel Corporation, AT32UC3A364S Datasheet - Page 566

• Manufacturer Part Number: AT32UC3A364S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A364S

• Flash (kbytes): 64 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

Figure 25-30. T=0 Protocol without Parity Error
Figure 25-31. T=0 Protocol with Parity Error
25.6.4.3
25.6.4.4
25.6.4.5
25.6.4.6
25.6.4.7
32072G–11/2011
Baud Rate
Baud Rate
Clock
I/O
Clock
RXD
Protocol T=1
Receive NACK Inhibit
Transmit Character Repetition
Receive Error Counter
Disable Successive Receive NACK
Start
Bit
Start
Bit
D0
parity error, as shown in
(NACK), by pulling the line low for a bit period within the guard time, resulting in the total charac-
ter length being incremented by one, see
it detects a parity error, and will set PARE if it receives a NACK.
In T=1 protocol, the character resembles an asynchronous format with only one stop bit. The
parity is generated when transmitting and checked when receiving. Parity errors set PARE.
The USART receiver keeps count of up to 255 errors in the Number Of Errors field in the Num-
ber of Error Register (NER.NB_ERRORS). Reading NER automatically clears NB_ERRORS.
The USART can be configured to ignore parity errors by writing a one to the Inhibit Non
Acknowledge bit (MR.INACK). Erroneous characters will be treated as if they were ok, not gen-
erating a NACK, loaded to RHR, and raising RXRDY.
The USART can be configured to automatically re-send a character if it receives a NACK. Writ-
ing a value other than zero to MR.MAX_ITERATION will enable and determine the number of
consecutive re-transmissions. If the number of unsuccessful re-transmissions equal
MAX_ITERATION, the iteration bit (CSR.ITER) is set. Writing a one to the Reset Iteration bit
(CR.RSTIT) will clear ITER.
The receiver can limit the number of consecutive NACK’s to the value in MAX_ITERATION. This
is enabled by writing a one to the Disable Successive NACK bit (MR.DSNACK). If the number of
NACK’s is about to surpass MAX_ITERATION, the character will instead be accepted as valid
and ITER is set.
D0
D1
D1
D2
D2
D3
D3
Figure
D4
D4
25-30. The receiver signals a parity error, aka non-acknowledge
D5
D5
D6
D6
Figure
D7
D7
25-31. The USART will not load data to RHR if
Parity
Bit
Parity
Bit
Time 1
Guard
Time 1
Guard
Error
Time 2
Guard
Time 2
Guard
Start
Next
Bit
Start
Bit
Repetition
D0
D1
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