AT32UC3A364S Atmel Corporation, AT32UC3A364S Datasheet - Page 211

• Manufacturer Part Number: AT32UC3A364S
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A364S

• Flash (kbytes): 64 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 110
• Ext Interrupts: 110
• Usb Transceiver: 1
• Usb Speed: Hi-Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 2
• Uart: 4
• Lin: 4
• Ssc: 1
• Sd / Emmc: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: AES
• Sram (kbytes): 128
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: Yes
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0 to 3.6
• Operating Voltage (vcc): 3.0 to 3.6
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 6
• Output Compare Channels: 18
• Input Capture Channels: 12
• Pwm Channels: 12
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

15.7
The SMC is programmed using the registers listed in
is used to program the parameters of the external device connected on it. In
denotes the chip select number. Sixteen bytes (0x10) are required per chip select.
The user must complete writing the configuration by writing anyone of the Mode Registers.
Table 15-8.
32072G–11/2011
0x0C + CS_number*0x10
0x00 + CS_number*0x10
0x04 + CS_number*0x10
0x08 + CS_number*0x10
User Interface
Offset
SMC Register Memory Map
Setup Register
Pulse Register
Cycle Register
Mode Register
Register
Table 15-8 on page
Register Name
SETUP
PULSE
CYCLE
MODE
211. For each chip select, a set of four registers
Table 15-8 on page
Read/Write
Read/Write
Read/Write
Read/Write
Access
211, “CS_number”
0x01010101
0x01010101
0x00030003
0x10002103
Reset
211