74F544 Fairchild Semiconductor, 74F544 Datasheet

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... Separate Latch Enable and Output Enable inputs are provided for each register to permit independent con- trol of inputting and outputting in either direction of data flow. The A outputs are guaranteed to sink 24 mA while the B outputs are rated for 64 mA. The 74F544 inverts data in both directions. Ordering Code: Order Number ...

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... A-to-B 3-STATE Outputs Functional Description The 74F544 contains two sets of eight D-type latches, with separate input and output controls for each set. For data flow from for example, the A-to-B Enable (CEAB) input must be LOW in order to enter data from A take data from B – ...

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Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to Ground Pin CC Input Voltage (Note 2) Input Current (Note 5.0 mA Voltage Applied to Output in HIGH State ...

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AC Electrical Characteristics Symbol Parameter t Propagation Delay PLH t Transparent Mode PHL Propagation Delay PLH t LEBA to A PHL n t Propagation Delay PLH t LEAB ...

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Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide 24-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide Package Number M24B Package Number MSA24 5 www.fairchildsemi.com ...

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...