9403APC Fairchild Semiconductor, 9403APC Datasheet
9403APC
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9403APC Summary of contents
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... TTL families. Ordering Code: Order Number Package Number 9403APC N24E 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...
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Unit Loading/Fan Out Pin Names D –D Parallel Data Inputs Serial Data Input S P Parallel Load Input L CPSI Serial Input Clock IES Serial Input Enable TTS Transfer to Stack Input OES Serial Output Enable TOS ...
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Functional Description As shown in the block diagram the 49403A consists of three sections Input Register with parallel and serial data inputs as well as control inputs and outputs for input handshak- ing and expansion 4-bit ...
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Functional Description (Continued) Transfer to the Stack—The outputs of Flip-Flops F feed the stack. A LOW level on the TTS input initiates a “fall-through” action. If the top location of the stack is empty, data is loaded into the stack ...
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Functional Description (Continued) EXPANSION Vertical Expansion—The 9403A may be vertically expanded to store more words without external parts. The interconnection is necessary to form a 46-word by 4-bit FIFO are shown in Figure 4. Using the same technique, and FIFO ...
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Functional Description (Continued) FIGURE 5. A Horizontal Expansion Scheme www.fairchildsemi.com FIGURE 6. A 31x16 FIFO Array 6 ...
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Functional Description (Continued) FIGURE 7. Serial Data Entry for Array of Figure 6 FIGURE 8. Serial Data Extraction for Array of Figure 6 7 www.fairchildsemi.com ...
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Functional Description (Continued) FIGURE 9. Final Position of a 496-Bit Serial Input FIGURE 10. Conceptual Diagram, Interlocking Circuitry www.fairchildsemi.com 8 ...
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Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias V Pin Potential to Ground Pin CC Input Voltage (Note 2) Input Current (Note 5.0 mA Voltage Applied to Output in HIGH State ...
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AC Electrical Characteristics Symbol Parameter t Propagation Delay, PHL Negative-Going CPSI to IRF Output t Propagation Delay, PLH Negative-Going TTS to IRF t Propagation Delay, PLH t Negative-Going PHL CPSO to Q Output S t Propagation Delay, PLH t Positive-Going ...
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AC Electrical Characteristics Symbol Parameter t Propagation Delay, PLH Positive-Going OES to ORE t Propagation Delay, PLH Positive-Going IES to Positive-Going IRF t Propagation Delay, PLH MR to IRF t Propagation Delay, PHL MR to ORE t Propagation Delay, PZH ...
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AC Operating Requirements Symbol Parameter t (H) Setup Time, HIGH or LOW Negative CPSI (H) Hold Time, HIGH or LOW CPSI (L) Set-Time, LOW ...
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Timing Waveforms Conditions: stack not full, IES, PL LOW FIGURE 11. Serial Input, Unexpanded or Master Operation Conditions: stack not full, IES HIGH when initiated, PL LOW FIGURE 12. Serial Input, Expanded Slave Operation Conditions: data in stack, TOP HIGH, ...
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Timing Waveforms (Continued) Conditions: data in stack, TOP HIGH, IES HIGH when initiated FIGURE 14. Serial Output, Slave Operation Conditions: IES LOW when initiated, OE, CPSO LOW; data available in stack FIGURE 15. Parallel Output, 4-Bit Word or Master in ...
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Timing Waveforms (Continued) Conditions: stack not full, IES LOW when initialized FIGURE 17. Parallel Load Mode, 4-Bit Word (Unexpanded) or Master in Parallel Expansion Conditions: stack not full, device initialized (Note 3) with IES HIGH FIGURE 18. Parallel Load, Slave ...
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Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-010, 0.400 Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at ...