PC87109VBE Nuvoton Technology Corporation of America, PC87109VBE Datasheet - Page 18
![no-image](/images/manufacturer_photos/0/4/485/nuvoton_technology_corporation_of_america_sml.jpg)
PC87109VBE
Manufacturer Part Number
PC87109VBE
Description
IC CONTROLLER ADV UART 32-LQFP
Manufacturer
Nuvoton Technology Corporation of America
Datasheet
1.PC87109VBE.pdf
(56 pages)
Specifications of PC87109VBE
Features
Transmit Deferral
Number Of Channels
2, DUART
Fifo's
16 Byte
Voltage - Supply
5V
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
Mounting Type
Surface Mount
Package / Case
32-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
*PC87109VBE
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
3.1.3 EIR/FCR - Event Identification/FIFO Control Registers
These registers share the same address.
EIR is accessed during CPU read cycles while FCR is accessed during CPU write cycles.
EIR - Event Identification Register, Read Only.
The function of this register changes depending upon whether the device is in extended or non-extended mode.
Non-Extended Mode
The function of EIR is the same as in the 16550. It returns an encoded value representing the highest priority pending interrupt.
access is complete. Table 3-3 shows the interrupt priorities and the EIR encoded values.
While a CPU access is occurring, the device records new interrupts, but it does not change the currently encoded value until the
Bits
Function
Reset State
B0
B2-1
B3
B5-4
B7-6
B2
B3
B4
B5
B6
B7
UART, Sharp-IR, SIR Modes
MIR, FIR, CEIR Modes
MIR, FIR Modes
LS_IE - Link Status Interrupt Enable.
LS_IE/TXHLT_IE - Link Status/Transmitter
Halted Interrupt Enable.
Reserved
Read/Write as 0.
DMA_IE - DMA Interrupt Enable.
SFIF_IE - ST_FIFO Interrupt Enable.
TMR_IE - Timer Interrupt Enable.
TXEMP_IE - Transmitter Empty Interrupt Enable.
IPF - Interrupt Pending Flag.
When this bit is 0, an interrupt is pending.
When it is 1, no interrupt is pending.
IPR [1-0] - Interrupt Priority.
When bit 0 is 0, these bits identify the highest priority pending interrupt.
RXFT - RX_FIFO Time-out.
In the 16450 mode this bit is always 0.
In the 16550 mode (FIFOs enabled), this bit is set when an RX_FIFO time-out occurred and the associated interrupt
is currently the highest priority pending interrupt.
These bits always return 0.
FEN [1-0]- FIFOs Enabled.
These bits are set to 1 when the FIFOs are enabled
(Bit 0 of FCR set to 1).
FEN1
B7
0
Figure 3-3. Event Identification Register, Non-Extended Mode
FEN0
B6
0
B5
0
0
18
B4
0
0
RXFT
B3
0
IPR1
B2
0
IPR0
B1
0
www.national.com
IPF
B0
1