PC87109VBE Nuvoton Technology Corporation of America, PC87109VBE Datasheet - Page 17

• Manufacturer Part Number: PC87109VBE
• Description: IC CONTROLLER ADV UART 32-LQFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of PC87109VBE

• Features: Transmit Deferral
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 5V
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *PC87109VBE

3.1 Bank 0
3.1.1 TXD/RXD - Transmit/Receive Data Ports
These ports share the same address.
TXD is accessed during CPU write cycles. It provides the write data path to the transmitter holding register when the FIFOs are
disabled, or to the TX_FIFO top location when the FIFOs are enabled.
RXD is accessed during CPU read cycles. It provides the read data path from the receiver holding register when the FIFOs are
disabled, or from the RX_FIFO bottom location when the FIFOs are enabled.
DMA cycles always access the transmitter and receiver holding registers or FIFOs, regardless of the selected bank.
3.1.2 IER - Interrupt Enable Register
This register controls the enabling of the various interrupts. Some interrupts are common to all operating modes, while others
are only available with specific modes. Bits 4 to 7 can be set in extended mode only. They are cleared in non-extended mode.
When a bit is set to 1, an interrupt is generated when the corresponding event occurs. In the non-extended mode most events
can be identified by reading the LSR and MSR registers. Reading the EIR register after the corresponding interrupt has been
generated can only identify the receiver high-data-level event. In the extended mode event flags in the EIR register identify
events. Upon reset, all bits are set to 0.
Note1: If the interrupt signal drives an edge-sensitive interrupt controller input, it is advisable to disable all interrupts by clearing all the IER
bits
Note 2: If an interrupt source must be disabled, the CPU can do so by clearing the corresponding bit in the IER register. However, if an
Note 3: If the LSR, MSR or EIR registers are to be polled, the interrupt sources which are identified via self-clearing bits should have their
Bits
Function
Reset State
B0
B1
generated. To avoid this problem, the clearing of any IER bit should be done during execution of the interrupt service routine. If
the interrupt controller is programmed for level-sensitive interrupts, the clearing of IER bits can also be performed outside the
interrupt service routine, but with the CPU interrupt disabled.
upon entering the interrupt routine, and re-enable them just before exiting it. This will guarantee proper interrupt triggering in the
interrupt controller in case one or more interrupt events occur during execution of the interrupt routine.
interrupt event occurs just before the corresponding enable bit in the IER register is cleared, a spurious interrupt may be
corresponding IER bits set to 0. This will prevent spurious pulses on the interrupt output pin.
RXHDL_IE - Receiver High-Data-Level Interrupt Enable.
TXLDL_IE - Transmitter Low-Data-Level Interrupt Enable.
TMR_IE
B7
0
Address
Offset
0
1
2
3
4
5
6
7
SFIF_IE
B6
0
IER
EIR/FCR
LCR/BSR
MCR
LSR
SPR/ASCR
TXD/RXD
Reserved
Register
Name
Figure 3-2. Interrupt Enable Register
TXEMP_IE
Table 3-2. Bank 0 Register Set
B5
0
Transmit/Receive Data Ports
Interrupt Enable Register
Event Identification/FIFO Control Registers
Link Control/Bank Select Registers.
Mode Control Register
Link Status Register
Reserved (return 0x30 upon read).
Scratch-pad /Auxiliary Status and control
Register
DMA_IE
17
B4
0
Description
res
B3
0
TXHLT_IE
LS_IE/
B2
0
TXLDL_IE
B1
0
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RXHDL_IE
B0
0