PC87109VBE Nuvoton Technology Corporation of America, PC87109VBE Datasheet - Page 4

• Manufacturer Part Number: PC87109VBE
• Description: IC CONTROLLER ADV UART 32-LQFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of PC87109VBE

• Features: Transmit Deferral
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 5V
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *PC87109VBE

List Of Figures
Figure 1-1. 32-Pin TQFP Package
Figure 1-2. Basic Configuration
Figure 2-1. Serial Data Stream Fromat
Figure 3-1. Register Bank Architecture
Figure 3-2. Interrupt Enable Register
Figure 3-3. Event Identification Register, Non-Extended Mode
Figure 3-4. Event Identification Register, Extended Mode
Figure 3-5. FIFO Control Register
Figure 3-6. Link Control Register
Figure 3-7. Mode Control Register, Non-Extended Model
Figure 3-8. Mode Control Register, Extended Mode
Figure 3-9. Link Status Register
Figure 3-10. Auxiliary Status and Control Register
Figure 3-11. Extended Control Register 1
Figure 3-12. DMA Control Signals Routing
Figure 3-13. Extended Control Register 2
Figure 3-14. Transmit FIFO Level
Figure 3-15. Receive FIFO Level
Figure 3-16. Infrared Control Register 1
Figure 3-17. Infrared Control Register 2
Figure 3-18. Frame Status Byte
Figure 3-19. Infrared Control Register 3
Figure 3-20. MIR Pulse Width Register
Figure 3-21. SIR Pulse Width Register
Figure 3-22. Beginning Flags/Preamble Length Register
Figure 3-23. Infrared Receiver Demodulator Control Register
Figure 3-24. Infrared Transmitter Modulator Control Register
Figure 3-25. CEIR Configuration Register
Figure 3-26. Infrared Configuration Register 1
Figure 3-27. Infrared Configuration Register 4
Figure 4-1. Control Signals Configuration Register
Figure 4-2. Control Signals Enable Register
Figure 4-3. Mode Control Register
Figure 5-1. Testing Specification Standard
Figure 5-2. Clock Timing
Figure 5-3. CPU Read Timing
Figure 5-4. CPU Write Timing
Figure 5-5. DMA Access Timing
Figure 5-6. UART, Sharp-IR and CEIR Timing
Figure 5-7. SIR, MIR and FIR Timing
Figure 5-8. IRSLn Write Timing
Figure 5-9. Reset Timing
Figure 6-1. Thin Plastic Quad Flat Pack
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