PC87109VBE Nuvoton Technology Corporation of America, PC87109VBE Datasheet - Page 11

• Manufacturer Part Number: PC87109VBE
• Description: IC CONTROLLER ADV UART 32-LQFP
• Manufacturer: Nuvoton Technology Corporation of America

Specifications of PC87109VBE

• Features: Transmit Deferral
• Number Of Channels: 2, DUART
• Fifo's: 16 Byte
• Voltage - Supply: 5V
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *PC87109VBE

2.4 IrDA 1.0 SIR Mode
This is the first operational mode that has been defined by
the IrDA committee and, similarly to Sharp-IR, it also
supports bi-directional data communication with a remote
device using infrared radiation as the transmission medium.
to 115.2 Kbaud. The format of the serial data is similar to
the UART data format. Each data word is sent serially
beginning with a zero value start bit, followed by 8 data bits,
and ending with at least one stop bit with a binary value of
one. Sending a single infrared pulse signals a zero. A one
is signaled by not sending any pulse. The width of each
pulse can be either 1.6 s or 3/16ths of a single bit time.
(1.6 s equals 3/16ths of a bit time at 115.2 Kbaud). This
way, each word begins with a pulse for the start bit.
The device operation, in IrDA 1.0 SIR, is similar to the
operation in UART mode. The main differences being
those data transfer operations are normally performed in
half-duplex fashion. Selection of the IrDA 1.0 SIR mode is
controlled by the MDSL bits in the MCR register when the
device is in extended mode or by the IR_SL bits in the
IRCR1 register when the device is in non-extended mode.
This prevents legacy software, running in non-extended
mode, from spuriously switching the device to UART mode,
when the software writes to the MCR register.
2.5 IrDA 1.1 MIR and FIR Modes
The PC87109 supports both IrDA 1.1 MIR and FIR modes,
with data rates of 576 Kbps, 1.152 Mbps and 4.0 Mbps.
Details on the frame format, encoding schemes, CRC
sequences, etc. are provided in the appropriate IrDA
documents. The MIR transmitter front-end section
performs bit stuffing on the outbound data stream and
places the Start and Stop flags at the beginning and end of
MIR frames. The MIR receiver front-end section removes
flags and “de-stuffs” the inbound bit stream, and checks for
abort conditions.
The FIR transmitter front-end section adds the Preamble as
well as Start and Stop flags to each frame and encodes the
transmit data into a 4PPM (Four Pulse Position Modulation)
data stream. The FIR receiver front-end section strips the
Preamble and flags from the inbound data stream and
decodes the 4PPM data while also checking for coding
violations.
Both MIR and FIR front-ends also automatically append
CRC sequences to transmitted frames and check for CRC
errors on received frames.
2.5.1 High Speed Infrared Transmit
When the transmitter is empty, if either the CPU or the
DMA controller writes data into the TX_FIFO, transmission
of a frame will begin. Frame transmission can be normally
completed by using one of the following methods:
1. S_EOT bit (Set End of Transmission)
IrDA 1.0 SIR allows serial communication at baud rates up
This method is used when data transfers are performed
in PIO mode. When the CPU sets the S_EOT bit before
writing the last byte into the TX_FIFO, the byte will be
tagged with an EOF indication. When this byte reaches
the TX_FIFO bottom, and is read by the transmitter front-
11
2. DMA TC Signal (DMA Terminal Count)
3. Frame Length Counter
While a frame is being transmitted, data must be written to
the TX_FIFO at a rate dictated by the transmission speed.
If the CPU or DMA controller fails to meet this requirement,
a transmitter under-run will occur, an inverted CRC is
appended to the frame being transmitted, and the frame is
terminated with a Stop flag. Data transmission will then
stop. Transmission of the inverted CRC will guarantee that
the remote receiving device will receive the frame with a
CRC error and will discard it.
Following an under-run condition, data transmission always
stops at the next frame boundary. The frame bytes from
the point where the under-run occurred to the end of the
frame will not be sent out to the external infrared interface.
Nonetheless, they will be removed from the TX_FIFO by
the transmitter and discarded. The under-run indication will
be reported only when the transmitter detects the end of
frame via one of the methods described above. The
software can do various things to recover form an under-
run condition. For example, it can simply clear the under-
run condition by writing a 1 into bit 6 of ASCR and re-
transmit the under-run frame later, or it can re-transmit it
immediately, before transmitting other frames.
If it chooses to re-transmit the frame immediately, it needs
to perform the following steps:
1.
2.
end, a CRC is appended to the transmitted DATA and
the frame is normally terminated.
This method is used when data transfers are performed
in DMA mode. It works similarly to the previous method
except that the tagging of the last byte of a frame occurs
when the DMA controller asserts the TC signal during the
write of the last byte to the TX_FIFO.
This method can be used when data transfers are
performed in either PIO or DMA mode. The value of the
FEND_MD bit in the IRCR2 register determines whether
the Frame Length Counter is effective in the PIO or DMA
mode. The counter is loaded from the Frame Length
Register (TFRL) at the beginning of each frame, and it is
decrements as each byte is transmitted. An EOF is
generated when the counter reaches zero. This method
allows a large data block to be automatically split into
equal-size back-to-back frames, plus a shorter frame that
is terminated by the DMA TC signal when an 8237 type
DMA controller is used.
An option is also provided to stop transmission at the end
of each frame. This happens when the transmitter frame-
end stop mode is selected (TX_MS bit in IRCR2 register
set to 1).
By using this option, the software can send frames of
different sizes without re-initializing the DMA controller
for each frame. After transmission of each frame, the
transmitter stops and generates an interrupt. The
software loads the length of the next frame into the TFRL
register and restarts the transmitter by clearing the
TXHFE bit in the ASCR register.
Disable DMA controller, if DMA mode was selected.
Read the TXFLV register to determine the number of
bytes in the TX_FIFO. (This is needed to determine
www.national.com