SC16C554DIB64,128 NXP Semiconductors, SC16C554DIB64,128 Datasheet - Page 24

• Manufacturer Part Number: SC16C554DIB64,128
• Description: IC UART QUAD SOT314-2
• Manufacturer: NXP Semiconductors

Specifications of SC16C554DIB64,128

• Number Of Channels: 4, QUART
• Fifo's: 16 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935270063128; SC16C554DIB64-T; SC16C554DIB64-T

Philips Semiconductors
9397 750 13132
Product data
7.2.1 IER versus Receive FIFO interrupt mode operation
7.2.2 IER versus Receive/Transmit FIFO polled mode operation
Table 9:
When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1)
are enabled, the receive interrupts and register status will reflect the following:
When FCR[0] = logic 1, resetting IER[0:3] enables the SC16C554/554D in the FIFO
polled mode of operation. Since the receiver and transmitter have separate bits in the
LSR, either or both can be used in the polled mode by selecting respective transmit or
receive control bit(s).
Bit
2
1
0
•
•
•
•
•
•
•
•
The receive data available interrupts are issued to the external CPU when the
FIFO has reached the programmed trigger level. It will be cleared when the FIFO
drops below the programmed trigger level.
FIFO status will also be reflected in the user accessible ISR register when the
FIFO trigger level is reached. Both the ISR register status bit and the interrupt will
be cleared when the FIFO drops below the trigger level.
The data ready bit (LSR[0]) is set as soon as a character is transferred from the
shift register to the receive FIFO. It is reset when the FIFO is empty.
LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
LSR[1:4] will provide the type of errors encountered, if any.
LSR[5] will indicate when the transmit FIFO is empty.
LSR[6] will indicate when both the transmit FIFO and transmit shift register are
empty.
LSR[7] will indicate any FIFO data errors.
Symbol
IER[2]
IER[1]
IER[0]
Interrupt Enable Register bits description
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Description
Receive Line Status interrupt.
Transmit Holding Register interrupt. This interrupt will be issued whenever
the THR is empty, and is associated with LSR[1].
Receive Holding Register interrupt. This interrupt will be issued when the
FIFO has reached the programmed trigger level, or is cleared when the
FIFO drops below the trigger level in the FIFO mode of operation.
Logic 0 = Disable the receiver line status interrupt (normal default
condition).
Logic 1 = Enable the receiver line status interrupt.
Logic 0 = Disable the transmitter empty interrupt (normal default
condition).
Logic 1 = Enable the transmitter empty interrupt.
Logic 0 = Disable the receiver ready interrupt (normal default condition).
Logic 1 = Enable the receiver ready interrupt.
Rev. 05 — 10 May 2004
SC16C554/554D
…continued
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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