SC16C554DIB64,128 NXP Semiconductors, SC16C554DIB64,128 Datasheet - Page 16
![IC UART QUAD SOT314-2](/photos/6/98/69856/568-64-lqfp_sot314-2_sml.jpg)
SC16C554DIB64,128
Manufacturer Part Number
SC16C554DIB64,128
Description
IC UART QUAD SOT314-2
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C554DIA68512.pdf
(55 pages)
Specifications of SC16C554DIB64,128
Number Of Channels
4, QUART
Fifo's
16 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935270063128
SC16C554DIB64-T
SC16C554DIB64-T
SC16C554DIB64-T
SC16C554DIB64-T
Philips Semiconductors
9397 750 13132
Product data
6.6 Hardware flow control
6.7 Software flow control
Table 6:
When automatic hardware flow control is enabled, the SC16C554/554D monitors the
CTS pin for a remote buffer overflow indication and controls the RTS pin for local
buffer overflows. Automatic hardware flow control is selected by setting EFR[6] (RTS)
and EFR[7] (CTS) to a logic 1. If CTS transitions from a logic 0 to a logic 1 indicating
a flow control request, ISR[5] will be set to a logic 1 (if enabled via IER[6,7]), and the
SC16C554/554D will suspend TX transmissions as soon as the stop bit of the
character in process is shifted out. Transmission is resumed after the CTS input
returns to a logic 0, indicating more data may be sent.
With the Auto RTS function enabled, an interrupt is generated when the receive FIFO
reaches the programmed trigger level. The RTS pin will not be forced to a logic 1
(RTS off), until the receive FIFO reaches the next trigger level. However, the RTS pin
will return to a logic 0 after the data buffer (FIFO) is unloaded to the next trigger level
below the programmed trigger. However, under the above described conditions, the
SC16C554/554D will continue to accept data until the receive FIFO is full.
When software flow control is enabled, the SC16C554/554D compares one or two
sequential receive data characters with the programmed Xon/Xoff or Xoff1,2
character value(s). If received character(s) match the programmed values, the
SC16C554/554D will halt transmission (TX) as soon as the current character(s) has
completed transmission. When a match occurs, the receive ready (if enabled via Xoff
IER[5]) flags will be set and the interrupt output pin (if receive interrupt is enabled) will
be activated. Following a suspension due to a match of the Xoff characters’ values,
the SC16C554/554D will monitor the receive data stream for a match to the Xon1,2
character value(s). If a match is found, the SC16C554/554D will resume operation
and clear the flags (ISR[4]).
Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0.
Following reset, the user can write any Xon/Xoff value desired for software flow
control. Different conditions can be set to detect Xon/Xoff characters and
suspend/resume transmissions. When double 8-bit Xon/Xoff characters are selected,
the SC16C554/554D compares two consecutive receive characters with two software
flow control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions
accordingly. Under the above described flow control mechanisms, flow control
characters are not placed (stacked) in the user accessible RX data buffer or FIFO.
In the event that the receive buffer is overfilling and flow control needs to be executed,
the SC16C554/554D automatically sends an Xoff message (when enabled) via the
serial TX output to the remote modem. The SC16C554/554D sends the Xoff1,2
Selected trigger level
(characters)
1
4
8
14
Flow control mechanism
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Rev. 05 — 10 May 2004
INT pin activation
1
4
8
14
Negate RTS or
send Xoff
4
8
12
14
SC16C554/554D
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Assert RTS or
send Xon
1
4
8
10
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