SC16C554DIB64,128 NXP Semiconductors, SC16C554DIB64,128 Datasheet - Page 17
![IC UART QUAD SOT314-2](/photos/6/98/69856/568-64-lqfp_sot314-2_sml.jpg)
SC16C554DIB64,128
Manufacturer Part Number
SC16C554DIB64,128
Description
IC UART QUAD SOT314-2
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C554DIA68512.pdf
(55 pages)
Specifications of SC16C554DIB64,128
Number Of Channels
4, QUART
Fifo's
16 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935270063128
SC16C554DIB64-T
SC16C554DIB64-T
SC16C554DIB64-T
SC16C554DIB64-T
Philips Semiconductors
9397 750 13132
Product data
6.8 Special feature software flow control
6.9 Hardware/software and time-out interrupts
characters as soon as received data passes the programmed trigger level. To clear
this condition, the SC16C554/554D will transmit the programmed Xon1,2 characters
as soon as receive data drops below the programmed trigger level.
A special feature is provided to detect an 8-bit character when EFR[5] is set. When
8-bit character is detected, it will be placed on the user-accessible data stack along
with normal incoming RX data. This condition is selected in conjunction with
EFR[0-3]. Note that software flow control should be turned off when using this special
mode by setting EFR[0-3] to a logic 0.
The SC16C554/554D compares each incoming receive character with Xoff2 data. If a
match exists, the received data will be transferred to the FIFO, and ISR[4] will be set
to indicate detection of a special character. Although the Internal Register Table
(Table
number of bits is dependent on the programmed word length. Line Control Register
bits LCR[0-1] define the number of character bits, i.e., either 5 bits, 6 bits, 7 bits or
8 bits. The word length selected by LCR[0-1] also determine the number of bits that
will be used for the special character comparison. Bit 0 in the X-registers corresponds
with the LSB bit for the receive character.
Three special interrupts have been added to monitor the hardware and software flow
control. The interrupts are enabled by IER[5-7]. Care must be taken when handling
these interrupts. Following a reset, if the transmitter interrupt is enabled, the
SC16C554/554D will issue an interrupt to indicate that the Transmit Holding Register
is empty. This interrupt must be serviced prior to continuing operations. The LSR
register provides the current singular highest priority interrupt only. It could be noted
that CTS and RTS interrupts have lowest interrupt priority. A condition can exist
where a higher priority interrupt may mask the lower priority CTS/RTS interrupt(s).
Only after servicing the higher pending interrupt will the lower priority CTS/TRS
interrupt(s) be reflected in the status register. Servicing the interrupt without
investigating further interrupt conditions can result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same
interrupt priority (when enabled by IER[0]). The receiver issues an interrupt after the
number of characters have reached the programmed trigger level. In this case, the
SC16C554/554D FIFO may hold more characters than the programmed trigger level.
Following the removal of a data byte, the user should re-check LSR[0] for additional
characters. A Receive Time Out will not occur if the receive FIFO is empty. The
time-out counter is reset at the center of each stop bit received or each time the
receive holding register (RHR) is read. The actual time-out value is 4 character time.
In the 16 mode for the PLCC68 package, the system/board designer can optionally
provide software controlled 3-State interrupt operation. This is accomplished by
INTSEL and MCR[3]. When INTSEL interface pin is left open or made a logic 0,
MCR[3] controls the 3-State interrupt outputs, INTA-INTD. When INTSEL is a logic 1,
MCR[3] has no effect on the INTA-INTD outputs, and the package operates with
interrupt outputs enabled continuously.
8) shows each X-Register with eight bits of character information, the actual
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Rev. 05 — 10 May 2004
SC16C554/554D
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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