SC16C554DIB64,128 NXP Semiconductors, SC16C554DIB64,128 Datasheet - Page 22

• Manufacturer Part Number: SC16C554DIB64,128
• Description: IC UART QUAD SOT314-2
• Manufacturer: NXP Semiconductors

Specifications of SC16C554DIB64,128

• Number Of Channels: 4, QUART
• Fifo's: 16 Byte
• Voltage - Supply: 2.5V, 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935270063128; SC16C554DIB64-T; SC16C554DIB64-T

Philips Semiconductors
7. Register descriptions
Table 8:
Shaded bits are only accessible when EFR[4] is set.
[1]
[2]
[3]
[4]
9397 750 13132
Product data
A2 A1 A0 Register Default
General Register Set
0
0
0
0
0
0
1
1
1
1
Special Register Set
0
0
Enhanced Register Set
0
1
1
1
1
The value shown represents the register’s initialized HEX value; X = n/a.
These registers are accessible only when LCR[7] = 0.
The Special Register set is accessible only when LCR[7] is set to a logic 1.
Enhanced Feature Register, Xon-1,2 and Xoff-1,2 are accessible only when LCR is set to ‘BF
0
0
0
1
1
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
0
1
0
0
1
0
1
SC16C554/554D internal registers
RHR
THR
IER
FCR
ISR
LCR
MCR
LSR
MSR
SPR
DLL
DLM
EFR
Xon-1
Xon-2
Xoff-1
Xoff-2
[3]
[2]
[4]
XX
XX
00
00
01
00
00
60
X0
FF
XX
XX
00
00
00
00
00
Table 8
The assigned bit functions are more fully defined in
[1]
Bit 7
bit 7
bit 7
CTS
interrupt
RCVR
trigger
(MSB)
FIFOs
enabled
divisor
latch
enable
0
FIFO
data
error
CD
bit 7
bit 7
bit 15
Auto
CTS
bit 7
bit 15
bit 7
bit 15
details the assigned bit functions for the SC16C554/554D internal registers.
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Bit 6
bit 6
bit 6
RTS
interrupt
RCVR
trigger
(LSB)
FIFOs
enabled
set
break
IR
enable
trans.
empty
RI
bit 6
bit 6
bit 14
Auto
RTS
bit 6
bit 14
bit 6
bit 14
Rev. 05 — 10 May 2004
Bit 5
bit 5
Xoff
interrupt
reserved reserved
INT
priority
bit 4
set parity even
0
trans.
holding
empty
bit 5
bit 5
bit 13
Special
char.
select
bit 5
DSR
bit 5
bit 13
bit 5
bit 13
Bit 4
bit 4
bit 4
Sleep
mode
INT
priority
bit 3
parity
loop back OP2,
break
interrupt
CTS
bit 4
bit 4
bit 12
Enable
IER[4:7],
ISR[4:5],
MCR[6]
bit 4
bit 12
bit 4
bit 12
bit 3
bit 3
bit 3
bit 3
bit 11
bit 3
bit 11
bit 3
bit 11
Bit 3
modem
status
interrupt
DMA
mode
select
INT
priority
bit 2
parity
enable
INTx
enable
framing
error
Cont-3
Tx, Rx
Control
CD
SC16C554/554D
Section 7.1
Hex
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
’.
Bit 2
bit 2
bit 2
receive
line status
interrupt
XMIT
FIFO reset
INT
priority
bit 1
stop bits
OP1
parity
error
bit 2
bit 2
bit 10
Cont-2 Tx,
Rx Control
bit 2
bit 10
bit 2
bit 10
RI
through
Bit 1
bit 1
bit 1
transmit
holding
register
RCVR
FIFO
reset
INT
priority
bit 0
word
length
bit 1
RTS
overrun
error
bit 1
bit 1
bit 9
Cont-1
Tx, Rx
Control
bit 1
bit 9
bit 1
bit 9
DSR
Section
Bit 0
bit 0
bit 0
receive
holding
register
FIFO
enable
INT
status
word
length
bit 0
DTR
receive
data
ready
bit 0
bit 0
bit 8
Cont-0
Tx, Rx
Control
bit 0
bit 8
bit 0
bit 8
CTS
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7.11.