SC16C554DIB64,128 NXP Semiconductors, SC16C554DIB64,128 Datasheet - Page 19
![IC UART QUAD SOT314-2](/photos/6/98/69856/568-64-lqfp_sot314-2_sml.jpg)
SC16C554DIB64,128
Manufacturer Part Number
SC16C554DIB64,128
Description
IC UART QUAD SOT314-2
Manufacturer
NXP Semiconductors
Datasheet
1.SC16C554DIA68512.pdf
(55 pages)
Specifications of SC16C554DIB64,128
Number Of Channels
4, QUART
Fifo's
16 Byte
Voltage - Supply
2.5V, 3.3V, 5V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
935270063128
SC16C554DIB64-T
SC16C554DIB64-T
SC16C554DIB64-T
SC16C554DIB64-T
Philips Semiconductors
9397 750 13132
Product data
6.11 DMA operation
6.12 Sleep mode
6.13 Loop-back mode
The SC16C554/554D FIFO trigger level provides additional flexibility to the user for
block mode operation. LSR[5,6] provide an indication when the transmitter is empty
or has an empty location(s). The user can optionally operate the transmit and receive
FIFOs in the DMA mode (FCR[3]). When the transmit and receive FIFOs are enabled
and the DMA mode is de-activated (DMA Mode 0), the SC16C554/554D activates the
interrupt output pin for each data transmit or receive operation. When DMA mode is
activated (DMA Mode 1), the user takes the advantage of block mode operation by
loading or unloading the FIFO in a block sequence determined by the preset trigger
level. In this mode, the SC16C554/554D sets the interrupt output pin when characters
in the transmit FIFOs are below the transmit trigger level, or the characters in the
receive FIFOs are above the receive trigger level.
The SC16C554/554D is designed to operate with low power consumption. A special
sleep mode is included to further reduce power consumption when the chip is not
being used. With EFR[4] and IER[4] enabled (set to a logic 1), the SC16C554/554D
enters the sleep mode, but resumes normal operation when a start bit is detected, a
change of state on any of the modem input pins RX, RI, CTS, DSR, CD, or a transmit
data is provided by the user. If the sleep mode is enabled and the SC16C554/554D is
awakened by one of the conditions described above, it will return to the sleep mode
automatically after the last character is transmitted or read by the user. In any case,
the seep mode will not be entered while an interrupt(s) is pending. The
SC16C554/554D will stay in the sleep mode of operation until it is disabled by setting
IER[4] to a logic 0.
The internal loop-back capability allows on-board diagnostics. In the loop-back mode,
the normal modem interface pins are disconnected and reconfigured for loop-back
internally. MCR[0-3] register bits are used for controlling loop-back diagnostic testing.
In the loop-back mode, OP1 and OP2 in the MCR register (bits 2-3) control the
modem RI and CD inputs, respectively. MCR signals DTR and RTS (bits 0-1) are
used to control the modem DSR and CTS inputs, respectively. The transmitter output
(TX) and the receiver input (RX) are disconnected from their associated interface
pins, and instead are connected together internally (see
CD, and RI are disconnected from their normal modem control input pins, and instead
are connected internally to RTS, DTR, OP2 and OP1. Loop-back test data is entered
into the transmit holding register via the user data bus interface, D0-D7. The transmit
UART serializes the data and passes the serial data to the receive UART via the
internal loop-back connection. The receive UART converts the serial data back into
parallel data that is then made available at the user data interface D0-D7. The user
optionally compares the received data to the initial transmitted data for verifying
error-free operation of the UART TX/RX circuits.
In this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational. However, the interrupts can only be read
using lower four bits of the Modem Status Register (MSR[0:3]) instead of the four
Modem Status Register bits 4-7. The interrupts are still controlled by the IER.
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Rev. 05 — 10 May 2004
SC16C554/554D
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Figure
8). The CTS, DSR,
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