SC28L198A1A,518 NXP Semiconductors, SC28L198A1A,518 Datasheet - Page 6

• Manufacturer Part Number: SC28L198A1A,518
• Description: IC UART OCTAL SOT189-3
• Manufacturer: NXP Semiconductors
• Type: Octal UART for 3.3 V and 5 V supply voltager

Specifications of SC28L198A1A,518

• Number Of Channels: 8
• Package / Case: 84-LCC (J-Lead)
• Features: False-start Bit Detection
• Fifo's: 16 Byte
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 0.4608 MBd
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 3 V
• Supply Current: 150 mA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V or 5 V
• Transmit Fifo: 16Byte
• Receive Fifo: 16Byte
• Transmitter And Receiver Fifo Counter: No
• Operating Supply Voltage (typ): 3.3/5V
• Package Type: PLCC
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 3V
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935261323518; SC28L198A1A-T; SC28L198A1A-T

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
2. For operating at elevated temperatures, the device must be derated based on +150 C maximum junction temperature.
3. Parameters are valid over specified temperature range. See ordering information table for applicable temperature range and operating
4. This product includes circuitry specifically designed for the protection of its internal devices from damaging effects of excessive static
Philips Semiconductors
Pin Description
NOTE: Many output pins will have very fast edges, especially when lightly loaded (less than 20 pf.) These edges may move as fast as 1 to 3 ns
fall or rise time. The user must be aware of the possible generation of ringing and reflections on improperly terminated interconnections. See
previous note on Sclk noise under pin assignments.
ABSOLUTE MAXIMUM RATINGS
NOTES:
2006 Aug 10
MNEMONIC
SClk
CEN
A(7:0)
D(7:0)
W_RN
DACKN
IRQN
IACKN
TD(a–h)
RD(a–h)
I/O0(a–h)
I/O1(a–h)
I/O2(a–h)
I/O3(a–h)
G
G
RESETN
X1/CCLK
X2
Power Supplies
T
T
V
V
P
P
Octal UART for 3.3 V and 5 V supply voltage
IN
OUT
A
STG
CC
SS
D
D
the functional operation of the device at these or any other conditions above those indicated in the Operation Section of this specification is
not implied.
supply range.
charge.
(1:0)
SYMBOL
0
TYPE
I
I
I
I/O
I
O
O
I
O
I
I/O
I/O
I/O
I/O
I
O
I
I
O
I
Operating ambient temperature range
Storage temperature range
Voltage from V
Voltage from any pin to Vss
Package Power Dissipation (PLCC)
Package Power Dissipation (LQFP)
Derate above 25 C (PLCC pkg.)
Derate above 25 C (LQFP pkg.)
Write Read not control: When high indicates that the host CPU will write to a 28L198 register or transmit FIFO.
DESCRIPTION
Host system clock. Used to time operations in the Host Interface and clock internal logic. Must be greater
than twice the frequency of highest X1, Counter/Timer, TxC (1x) or RxC (1x) input frequency.
Chip select: Active low. When asserted, allows I/O access to OCTART registers by host CPU. W_RN signal
indicates direction. (Must not be active in IACKN cycle)
Address lines (A[6] is NOT used. See ”Host Interface” )
8–bit bi–directional data bus. Carries command and status information between 28L198 and the host CPU.
Used to convey parallel data for serial I/O between the host CPU and the 28L198
When low, indicates a read cycle. 0 = Read; 1 = Write
Data Acknowledge: Active low. When asserted, it signals that the last transfer of the D lines is complete.
Open drain.
Interrupt Request: Active low. When asserted, indicates that the 28L198 requires service for pending inter-
rupt(s). Open drain.
Interrupt Acknowledge: Active low. When asserted, indicates that the host CPU has initiated an interrupt ac-
knowledge cycle. (Do not use CEN in an IACKN cycle)
Transmit Data: Serial outputs from the 8 UARTs.
Receive Data: Serial inputs to the 8 UARTs
Input/Output 0: Multi–use input or output pin for the UART.
Input/Output 1: Multi–use input or output pin for the UART.
Input/Output 2: Multi–use input or output pin for the UART.
Input/Output 3: Multi–use input or output pin for the UART.
Global general purpose inputs, available to any/all channels.
Global general purpose outputs, available from any channel.
Master reset: Active Low. Must be asserted at power up and may be asserted at other times to reset and re-
start the system. See “Reset Conditions” at end of register map. Minimum width 10 SCLK.
Crystal 1 or Communication Clock: This pin may be connected to one side of a 2–8 MHz crystal. It may alter-
natively be driven by an external clock in this frequency range. Standard frequency = 3.6864 MHz
Crystal 2: If a crystal is used, this is the connection to the second terminal. If a clock signal drives X1, this pin
must be left unconnected.
8 pins total 6 pins for Vss, 2 pins for V
CC
to Vss
1
4
PARAMETER
2
CC
6
–0.5 to Vcc + 0.5
–65 to +150
–0.5 to +7.0
See Note 3
RATING
3.78
2.08
30
17
SC28L198
Product data sheet
mW/ C
mW/ C
UNIT
ºC
ºC
W
W
V
V