SC28L202A1DGG/G:11 NXP Semiconductors, SC28L202A1DGG/G:11 Datasheet - Page 32

• Manufacturer Part Number: SC28L202A1DGG/G:11
• Description: IC UART DUAL W/FIFO 56-TSSOP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L202A1DGG/G:11

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 256 Byte
• Voltage - Supply: 3.3V, 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 56-TFSOP (0.240", 6.10mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935279792112; SC28L202A1DGG/G; SC28L202A1DGG/G

Philips Semiconductors
COMMAND REGISTER EXTENSION TABLE A and B
Commands 0x0E, 0x0F, 0x1F (marked with ) are global and exist only in channel A’s register space.
2005 Nov 01
Channel
Command
Code
CR[4:0]
0 0000
0 0001
0 0010
0 0011
0 0100
0 0101
0 0110
0 0111
0 1000
0 1001
0 1010
0 1011
0 1100
0 1101
0 1110
0 1111
10111 Host Xoff (or transmitter pause) command (CRTXoff). This
command allows tight host CPU control of the flow control of the
channel transmitter. When interrupted for receipt of a Xoff
character by the receiver, the host may stop transmission of
further characters by the channel transmitter by issuing the Host
Xoff command. Any character that has been transferred to the
TxD shift register will complete its transmission, including the stop
bit before the transmitter pauses. Even though the transmitter is
paused it is still able to send Xon/Xoff by the request of its
associated receiver.
11000 Cancel Host transmit flow control command. Issuing this
command will cancel a previous command to transmit a flow
control character if the flow control character is not yet loaded into
the TxD Shift Register. If there is no character waiting for
transmission or if its transmission has already begun, then this
command has no effect and the character will be sent.
Dual UART
Channel
Command
Description
NOP
Set MR pointer to 1
Reset Receiver
Reset Transmitter
Reset Error Status
Reset Break Change Interrupt
Begin Transmit Break
End Transmit Break
Assert RTSN (I/O0 B or I/O1 B)
Negate RTSN (I/O0 B or I/O1 B)
Set C/T Receiver time-out mode on
Set MR pointer to 0
Set C/T Receiver time-out mode off
Block Error Status on RxFIFO load
Power Down Mode On
Disable Power Down Mode
Channel
Command Code
CR[4:0]
1 0000
1 0001
1 0010
1 0011
1 0100
1 0101
1 0110
1 0111
1 1000
1 1001
1 1010
1 1011
1 1100
1 1101
1 1110
1 1111
26
11001 Reserved
11010 Reserved
11011 Reset Address Recognition Status. This command clears
the interrupt status that was set when an address character was
recognized by a disabled receiver operating in the special mode.
11100 Reserved
11101 Block error status accumulates on FIFO read (Default
State)
11110 Reset to ‘C92’ Register Set
11111 Reserved for channel B, for channel A: executes a chip
wide reset. Executing this command in channel a is equivalent to
a hardware reset with the RESET(N) pin. Executing in channel B
has no effect.
Channel
Command
Description
Transmit Xon
Transmit Xoff
Start C/T
Stop C/T
Reserved
Reserved
Transmitter Resume Command (CRXoffRe)
Host Xoff Command (CRTXoff)
Cancel Transmit X Char Command (CRTX)
Reserved
Reserved
Reset Address Recognition Status
Reserved
Block Error Status on RxFIFO Read
Reserved
Reset Device as a Hardware reset. Reserved in channel B*
SC28L202
Product data sheet