SC28L202A1DGG/G:11 NXP Semiconductors, SC28L202A1DGG/G:11 Datasheet - Page 13

• Manufacturer Part Number: SC28L202A1DGG/G:11
• Description: IC UART DUAL W/FIFO 56-TSSOP
• Manufacturer: NXP Semiconductors
• Series: IMPACTr

Specifications of SC28L202A1DGG/G:11

• Features: False-start Bit Detection
• Number Of Channels: 2, DUART
• Fifo's: 256 Byte
• Voltage - Supply: 3.3V, 5V
• With Parallel Port: Yes
• With Auto Flow Control: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Package / Case: 56-TFSOP (0.240", 6.10mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935279792112; SC28L202A1DGG/G; SC28L202A1DGG/G

Philips Semiconductors
interrupt parameters and for writing to and reading from FIFOs
without explicitly addressing them.
The CIR will load with 0x00 if IACKN or Update CIR is asserted
when the arbitration circuit is NOT asserting an interrupt. In this
condition there is no arbitration value that exceeds the threshold
value. When Interrupt vector modification is active in this situation
the interrupt vector bits associated with the CIR will all be zero. A
zero type field indicates nothing with in the DUART is requiring
processor service.
NOTE: IACKN is essentially a special read action where the value of
the interrupt vector is presented to the data bus.
Timing Circuit
Crystal Oscillator
The crystal oscillator operates directly from a crystal, tuned between
7.0 MHz and 16.2 MHz connected across the X1/Sclk and X2 inputs
with a minimum of external components. BRG values listed for the
clock select registers correspond to a 14.7456 MHz crystal
frequency. Use of different frequencies will change the ‘standard’
baud rates by precisely the ratio of 14.7456 MHz to the different
crystal frequency.
An external clock up to 50 MHz frequency range may be connected
to X1/Sclk pin. If an external clock is used instead of a crystal,
X1/Sclk must be driven and X2 left floating or driving a load of not
more than 2 CMOS or TTL equivalents. The X1/Sclk clock serves as
the basic timing reference for the baud rate generator (BRG) and is
available to the programmable BRG (PBRG), counter-timers, control
logic and the UART receivers and transmitters.
Baud Rate Generator BRG
The baud rate generator operates from the oscillator or external
X1/Sclk clock input and generates 27 commonly used data
communications baud rates (including MIDI) ranging from 50 baud
to 921.6K baud. These common rates may be increased (up to
3000K baud) when faster clocks are used on the X1/Sclk clock
input. (See Receiver and Transmitter Clock Select Register
descriptions.) All of these are available simultaneously for use by
any receiver or transmitter. The clock outputs from the BRG are at
16X the actual baud rate.
Please see counter timer description for a description of the
frequency error that the asynchronous protocol may tolerate.
Depending on character length it varies from 4.1% to 6.7%.
Counter-Timer
The two Counter/Timers are programmable 16 bit dividers that are
used for generating miscellaneous clocks or generating timeout
periods or counting characters received by the receivers. Interrupts
may be generated any time the counter passes through 0x00. These
clocks may be used by any or all of the receivers and transmitters in
the DUART or may be directed to an I/O pin for miscellaneous use.
Counter/Timer programming
The counter timer is a 16-bit programmable divider that operates in
one of four modes: character count, counter, timer, and time out.
Character count counts characters. The timer mode generates a
square wave. In the counter mode it generates a time delay. In the
time out mode it monitors the time between received characters.
The C/T uses the numbers loaded into the Counter/Timer Lower
Register (CTPL) and the Counter/Timer Upper Register (CTPU) as
its divisor. The counter timer is controlled with six commands:
Start/Stop C/T, Read/Write Counter/Timer lower register and
Read/Write Counter/Timer upper register. These commands have
slight differences depending on the mode of operation. Please see
the detail of the commands under the CTPL/CTPU Register
descriptions.
2005 Nov 01
Dual UART
7
Whenever the these timers are selected via the receiver or
transmitter Clock Select register their output will be configured as a
16x clock for the respective receiver or transmitter. Therefore one
needs to program the timers to generate a clock 16 times faster than
the data rate. The formula for calculating ’n’, the number loaded to
the CTPU and CTPL registers, based on a particular input clock
frequency is shown below.
For the timer mode the formula is as follows:
(If the pulse mode is selected, then ‘2’ in the divisor should be ‘1’.
This doubles the C/T output speeds for any given input clock.)
NOTE: ‘n’ may assume a value of 1. In previous Philips data
communications controllers this value was not allowed. The
Counter/Timer Clock Select Register (CTCS) controls the
Counter/Timer input frequency.
The frequency generated from the above formula will be at a rate 16
times faster than the desired baud rate. The transmitter and receiver
state machines include divide by 16 circuits, which provide the final
frequency and provide various timing edges used in the qualifying
the serial data bit stream. Often this division will result in a
non-integer value: 26.3 for example. One may only program integer
numbers to a digital divider. There for 26 would be chosen. If 26.7
were the result of the division then 27 would be chosen. This gives a
baud rate error of 0.3/26.3 or 0.3/26.7 that yields a percentage error
of 1.14% or 1.12% respectively, well within the ability of the
asynchronous mode of operation. Higher input frequency to the
counter reduces the error effect of the fractional division.
One should be cautious about the assumed benign effects of small
errors since the other receiver or transmitter with which one is
communicating may also have a small error in the precise baud rate.
In a ‘clean’ communications environment using one start bit, eight
data bits and one stop bit the total difference allowed between the
transmitter and receiver frequency is approximately 4.6%. Less than
eight data bits will increase this percentage.
Programmable Baud Rate Generators. PBRG
Two PBRG Counters (Used only for random baud rate generation)
The two PBRG Timers are programmable 16 bit dividers that are
used for generating miscellaneous clocks. These clocks may be
used by any or all of the receivers and transmitters in the SC28L202
or output to the general purpose I/O pins.
Each timer unit has eight different clock sources available to it as
described in the PBRG clock source Register. Note that the timer
run and stop controls are also contained in this register. The PBRG
counters generate a symmetrical square wave whose half period is
equal in time to the division of the selected PBRG Timer clock
source by the number loaded to the PBRGPU and PBRGPL Preset
Registers. Thus, the output frequency will be the clock source
frequency divided by twice the 16 bit value loaded to these registers.
This is the result of counting down once for the high portion of the
output wave and once for the low portion.
Whenever the these timers are selected via the receiver or
transmitter Clock Select register their output will be configured as a
16x clock for the respective receiver or transmitter. Therefore one
needs to program the timers to generate a clock 16 times faster than
the data rate. The formula for calculating ’n’, the number loaded to
the PBRGPL and PBRGPU registers, is the same as shown above.
n
(2
C/T clock input frequency
16
(desired baud rate))
SC28L202
Product data sheet