PSB 21393 H V1.3 Infineon Technologies, PSB 21393 H V1.3 Datasheet - Page 112

• Manufacturer Part Number: PSB 21393 H V1.3
• Description: IC CODEC W/TRANSCEIVER MQFP-44
• Manufacturer: Infineon Technologies
• Series: SCOUT™r

Specifications of PSB 21393 H V1.3

• Function: CODEC
• Interface: IOM-2, SCI, UPN
• Number Of Circuits: 1
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 27mA
• Mounting Type: Surface Mount
• Package / Case: 44-BQFP
• Includes: Activation and Deactivation, Channel Handler, DTMF / Tone / Ringing Generator, HDLC Controller, Speakerphone, UPN Transceiver
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power (watts): -
• Operating Temperature: -
• Other names: PSB21393HV1.3XT; PSB21393HV13XP; SP000007533; SP000007534

Data Sheet
3.5
This non-HDLC mode is selected by setting MODE2...0 to ’100’. In extended transparent
mode fully transparent data transmission/reception without HDLC framing is performed
i.e. without FLAG generation/recognition, CRC generation/check, bitstuffing mechanism.
This allows user specific protocol variations.
3.5.1
The transmitter sends the data out of the FIFO without manipulation. Transmission is
always IOM-frame aligned and byte aligned, i.e. transmission starts in the first selected
channel (B1, B2, D, according to the setting of register HCI_CR in the IOM Handler) of
the next IOM frame.
The FIFO indications and commands are the same as in other modes.
If the microcontroller sets XTF & XME the transmitter responds with an XPR interrupt
after sending the last byte, then it returns to its idle state (sending continuous ‘1’).
If the collision detection is enabled (MODE.DIM = ’0x1’) the stop go bit (S/G) can be used
as clear to send indication as in any other mode. If the S/G bit is set to ’1’ (stop) during
transmission the transmitter responds always with an XMR (transmit message repeat)
interrupt.
If the microcontroller fails to respond to a XPR interrupt in time and the transmitter runs
out of data then it will assert an XDU (transmit data underrun) interrupt.
3.5.2
The reception is IOM-frame aligned and byte aligned, like transmission, i.e. reception
starts in the first selected channel (B1, B2, D, according to the setting of register HCI_CR
in the IOM Handler) of the next IOM frame. The FIFO indications and commands are the
same as in others modes.
All incoming data bytes are stored in the RFIFO and additionally made available in
RSTA.
Extended Transparent Mode
Transmitter
Receiver
102
HDLC Controller
PSB 21391
PSB 21393
2001-03-07