PSB 21393 H V1.3 Infineon Technologies, PSB 21393 H V1.3 Datasheet
PSB 21393 H V1.3
Specifications of PSB 21393 H V1.3
PSB21393HV13XP
SP000007533
SP000007534
Related parts for PSB 21393 H V1.3
PSB 21393 H V1.3 Summary of contents
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... Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies failure of such components can reasonably be expected to cause the failure of that life-support device or system affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body support and/or maintain and sustain and/or protect human life ...
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... Figure 85 modified 233 Timings added 236 Power supply currents added For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://www.infineon.com 2001-03-07 Prel. Data Sheet 09. ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 2.3.4.1 B1-, B2- and D-Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 3.3.1.3 Data Transmission Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99 3.3.2 Transmit ...
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Table of Contents 4.8.3 Reference Tables for the Register and CRAM Locations . . . . . . . . . . .148 5 Clock Generation . . . . . . . . . . . . . . ...
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Table of Contents 7.1.8 ISTA - Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 ...
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Table of Contents 8 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Overview The SCOUT-P or SCOUT-PX respectively integrates all necessary functions for the completion of a cost effective digital voice terminal solution. Please note: Throughout the whole document “SCOUT and “SCOUT The SCOUT combines the functionality of the ARCOFI Codec ...
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Comparison of the SCOUT with the two chip solution SmartLink -P and ARCOFI-BA; -SP Operating modes Supply voltage Technology Package Transceiver Transformer ratio for receiver and transmitter Transceiver Output Driver Test loops Microcontroller Interface Microcontroller clock Register address space Codec ...
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IOM-2 IOM-2 Interface Monitor channel programming C/I channels Layer 1 state machine State machine in software IDSL (144kBit/s) HDLC support FIFO size Undervoltage detection Reset Sources Pulse width output LCD contrast Codec Analog inputs Band gap reference Max. AFE gain ...
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Speakerphone Status indication AGC initialization Voice data manipulation Voice data formats Mask register for voice data Provided Tone Generator Output Direct tone generator output to loudspeaker Saturation amplification of tone filter, i.e. CRAM Parameter GE Data Sheet SCOUT Register status ...
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Siemens Codec with U SCOUT-P, SCOUT-PX Version 1.3 1.1 Features • Serial control interface (SCI) • IOM-2 interface in TE mode, single/double clock, two serial data strobe signals • Various possibilities of microcontroller data access, data control and data manipulation ...
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FIFO buffer with 64 bytes per direction and programmable FIFO thresholds for efficient transfer of data packets • D-channel access control • Implementation of IOM-2 MONITOR and C/I-channel protocol to control peripheral devices • Realization of layer 1 state ...
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Pin Configuration VDDSEL 34 VDDDET DDA V 37 SSA 38 V REF BGREF 39 AXI 40 41 MIN2 MIP2 42 MIN1 43 44 MIP1 Figure 1 Pin Configuration Data Sheet ...
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Logic Symbol REF BGREF AXI MIN1 MIP2 MIN2 HOP HON LSP LSN separate power pins separate ground pins SS Figure 2 Logic Symbol of the SCOUT in ...
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Pin Definitions and Function Table 1 Pin No. Symbol Input (I) Output (O) Open Drain (OD – DDL V 16 – DDD V 36 – DDA V 1 – DDP V 27 – DDPLL 30 V – ...
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Table 1 Pin No. Symbol Input (I) Output (O) Open Drain (OD) 32 LIa I/O 33 LIb I/O 13 XTAL2 OI 14 XTAL1 I 15 EAW INT OD 12 MCLK O 18 SCLK I 19 ...
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Table 1 Pin No. Symbol Input (I) Output (O) Open Drain (OD REF 39 BGREF I/O 40 AXI I 44 MIP1 I 43 MIN1 I 42 MIP2 I 41 MIN2 I 5 HOP O 6 HON O ...
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Typical Applications The SCOUT can be used in a variety of applications like • PBX voice terminal (Figure 3) • PBX voice terminal with speakerphone (Figure 4) • PBX voice terminal as featurephone with acoustic echo cancellation (Figure 5) ...
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Figure 4 PBX Voice Terminal with Speakerphone Figure 5 PBX Voice Terminal as Featurephone with Acoustic Echo Cancellation Data Sheet SCOUT-PX SCI µC SCOUT-P IOM-2 SCI µC ACE 13 PSB 21391 PSB 21393 Overview U Interface PN voice_te_upn.vsd U Interface ...
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Fax Figure 6 PBX Voice Terminal with Tip/Ring Extension U Terminal 2 PN Figure 7 U -Terminal Repeater PN Data Sheet SCOUT-PX IOM-2 SLIC ARCOFI-BA SCOUT-PX IOM-2 SmartLink-P µC PSB 2197 TR-Mode U Terminal PSB 21391 PSB ...
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S/T Interface Figure 8 U -Terminal with S/T- Interface Option PN Data Sheet SCOUT-PX IOM-2 SCI SBCX µC PEB 2081 15 PSB 21391 PSB 21393 Overview U Interface PN upn_te_st_upn.vsd 2001-03-07 ...
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General Functions and Device Architecture Figure 9 shows the architecture of the SCOUT containing the following functional blocks: • U interface transceiver with SmartLink PSB 2197 or ISAC-P TE PSB 2196 PN functionality respectively • Serial microcontroller interface • ...
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Figure 9 Architecture of the SCOUT Data Sheet 17 PSB 21391 PSB 21393 Overview 2001-03-07 ...
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Interfaces The SCOUT provides the following interfaces: • Serial microcontroller interface together with a reset and microcontroller clock generation. • IOM-2 interface as an universal backplane for terminals • U interface towards the two wire subscriber line PN • ...
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Microcontroller Interface The SCOUT supports a serial microcontroller interface. For applications where no controller is connected to the SCOUT microcontroller interface programming is done via the IOM-2 MONITOR channel from a master device. In such applications the SCOUT operates ...
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Serial Control Interface (SCI) The serial control interface (SCI) is compatible to the SPI interface of Motorola or Siemens C510 family of microcontrollers. The SCI consists of 4 lines: SCLK, SDX, SDR and CS. Data are transferred via the ...
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Figure 10 Serial Control Interface Timing Data Sheet 21 PSB 21391 PSB 21393 Interfaces 2001-03-07 ...
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Programming Sequences The principle structure of a read/write access to the SCOUT registers via the serial control interface is shown in figure 11. write sequence: header SDR 7 read sequence: header SDR 7 SDX Figure 11 Serial Command Structure ...
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Table 3 Header Byte Code Adr-Data-Data-Data Header 00 : ARCOFI Compatible Sequence H This programming sequence is compatible to the SOP, COP and XOP command sequences of the ARCOFI. It ...
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Header Interleaved A-D-A-D Sequences H H The interleaved A-D-A-D sequences give direct read/write access to the address range 00 -6F (header the CRAM range have any length. This mode ...
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Header 43 : Read-/Write- only A-D-D-D Sequence H This mode (header 43 ) can be used for a fast access to the HDLC FIFO data. Any H address (rdadr, wradr) in the range between 00h and 1F gives access to ...
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Interrupt Structure and Logic Special events in the SCOUT are indicated by means of a single interrupt output, which requests the host to read status information from the SCOUT or transfer data from/to the SCOUT. Since only one INT ...
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Five interrupt bits in the ISTA register point at interrupt sources in the HDLC Controller (HDLC), Monitor- (MOS) and C/I- (CIC) handler, the transceiver (TRAN) and the synchronous transfer (ST). The timer interrupt (TIN) and the watchdog timer overflow (WOV) ...
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Microcontroller Clock Generation The microcontroller clock is provided by the pin MCLK. Five clock rates are selectable by a programmable prescaler (see chapter clock generation figure 78) which is controlled by the MODE1.MCLK bit corresponding following table. By setting ...
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IOM-2 Interface The SCOUT supports the IOM-2 interface in terminal mode with single clock and double clock. The IOM-2 interface consists of four lines: FSC, DCL, DD and DU. The rising edge of FSC indicates the start of an ...
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IOM-2 Frame Structure The frame structure on the IOM-2 data ports (DU,DD) in IOM-2 terminal mode is shown in figure 14 . Figure 14 IOM -2 Frame Structure in Terminal Mode The frame is composed of three channels • ...
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IOM-2 Handler The IOM-2 handler offers a great flexibility for handling the data transfer between the different functional units of the SCOUT and voice/data devices connected to the IOM-2 interface. Additionally it provides a microcontroller access to all time ...
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Figure 15 Architecture of the IOM Handler Data Sheet 32 PSB 21391 PSB 21393 Interfaces 2001-03-07 ...
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Controller Data Access (CDA) The IOM-2 handler provides with its four controller data access registers (CDA10, CDA11, CDA20, CDA21) a very flexible solution for the access to the 12 IOM-2 time slots by the microcontroller. The functional unit CDA ...
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TSa 0 1 Enable output input (EN_O0) (EN_I0) CDAx0 1 0 TSa a,b = 0...11 Figure 16 Data Access via CDAx0 and CDAx1 register pairs 2.2.2.1.1 Looping and Shifting Data Figure 17 gives examples ...
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Looping Data b) Shifting Data c) Switching Data . Figure 17 Examples for Data Access via CDAxy Registers a) Looping Data b) Shifting Data c) Switching Data Data Sheet TSa TSb CDAx0 CDAx0 .TSS: TSa ...
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Monitoring Data Figure 18 gives an example for monitoring of two IOM-2 time slots each simultaneously. For monitoring on DU and/or DD the channel registers with even numbers (CDA10, CDA20) are assigned to time slots ...
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Synchronous Transfer While looping, shifting and switching (see figure 21 and 22) the data can be accessed by the controller between the synchronous transfer interrupt (STI) and the synchronous transfer overflow interrupt (STOV). The microcontroller access to the CDAxy ...
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STI interrupt generated : STOV interrupt generated for a not acknowledged STI interrupt a) Interrupts for data access to time slot 0 (B1 after reset), MSTI.STI10 and MSTI.STOV10 enabled xy: CDA_TDSPxy.TSS: MSTI.STIxy: MSTI.STOVxy: TS11 b) Interrupts for data ...
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Figure 21 shows the timing of looping TSa TSa 0...11) via CDAxy register. TSa is read in the CDAxy register from DU and is written one frame later on DD ...
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Figure 22 shows the timing of shifting data from TSa to TSb on DU(DD). In figure 22a) shifting is done in one frame because TSa and TSb didn’t succeed direct one another (a,b = 0...9 and b a+2) In figure ...
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Serial Data Strobe Signal and strobed Data Clock For time slot oriented standard devices connected to the IOM-2 interface the SCOUT provides two independent data strobe signals SDS1 and SDS2. The SDS2 function is shared with the RSTO function ...
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FSC DD, MON0 TS0 TS1 SDS1,2 (Example1) SDS1,2 (Example2) SDS1,2 (Example3) Example 1: TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 Example 2: TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 Example 3: TSS ENS_TSS ENS_TSS+1 ENS_TSS+3 Figure 23 Data Strobe Signal Data Sheet M M ...
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Strobed IOM-2 Bit Clock The strobed IOM bit clock is active during the programmed window (see chapter 7.2.8). Outside the programmed window a ’0’ is driven. Two examples are shown in figure 24. FSC DD, TS0 TS1 ...
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IOM-2 Monitor Channel The IOM-2 MONITOR channel (see figure 14) is utilized for information exchange between the SCOUT and other devices connected to the MONITOR channel. The MONITOR channel data can be controlled by the bits in the MONITOR ...
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The MONITOR channel can be used in following applications which are illustrated in figure 25: • master device the SCOUT can program and control other devices attached to the IOM-2 which do not need a microcontroller interface e.g. ...
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The MONITOR channel protocol is described In the following section and illustrated in Figure 26. The relevant control and status bits for transmission and reception are listed in table 5 and table 6. Table 5 Transmission of MONITOR Data Control/ ...
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Transmission µC MIE=1 MOX=ADR MXC=1 MAC=1 MDA Int. MOX=DATA1 MDA Int. MOX=DATA2 MDA Int. MXC=0 MAC=0 Figure 26 MONITOR Channel Protocol (IOM-2) Data Sheet MON ADR ADR 0 ADR 0 ADR 0 DATA1 1 ...
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Before starting a transmission, the microcontroller should verify that the transmitter is inactive, i.e. that a possible previous transmission has been terminated. This is indicated by a ’0’ in the MONITOR Channel Active MAC status bit. After having written the ...
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The MONITOR transfer protocol rules are summarized in the following section • A pair of MX and MR in the inactive state for two or more consecutive frames indicates an idle state or an end of transmission. • A start ...
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MX/MR Treatment in Error Case: In the master mode the MX/MR bits are under control of the microcontroller through MXC or MRC respectively. An abort is indicated by an MAB interrupt or MER interrupt respectively. In the slave mode the ...
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IOM -2 Frame No (DU (DD) 0 Figure 29 Monitor Channel, normal End of Transmission 2.2.4.3 MONITOR Channel Programming as a Master Device As a master device the SCOUT can program and control other devices ...
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SCOUT. The lower nibble distinguishes between a programming command or an identification command. Identification Command In order to be able to identify unambiguously different hardware designs of the SCOUT by software, the ...
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MONITOR Time-Out Procedure To prevent lock-up situations in a MONITOR transmission a time-out procedure can be enabled by setting the time-out bit (TOUT) in the MONITOR configuration register (MCONF). An internal timer is always started when the transmitter must ...
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C/I Channel Handling The Command/Indication channel carries real-time status information between the SCOUT and another device connected to the IOM. 1) One C/I channel (called C/I0) conveys the commands and indications between the layer-1 and the layer-2 parts of ...
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If several consecutive codes are detected, only the first and the last code is obtained at the first and second register read, respectively. For CIR1 no FIFO is available. The actual code of the received C/I channel 1 is always ...
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D-Channel Access Control D-channel access control was defined to guarantee all connected HDLC controllers a fair chance to transmit data in the D-channel. Collisions are possible on the IOM-2 interface, if there is more than one HDLC controller connected. ...
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The arbitration mechanism is implemented in the last octet in IOM channel 2 of the IOM- 2 interface (see figure 33). An access request to the TIC bus may either be generated by software ( P access to the C/I ...
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The availability of the line interface D channel is indicated in bit 5 "Stop/Go" (S/G) of the DD last octet of channel 2 (figure 34). S stop S Figure 34 Structure of ...
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Activation/Deactivation of IOM-2 Interface The IOM-2 interface can be switched off in the inactive state, reducing power consumption to a minimum. In this deactivated state is FSC = ’1’, DCL = ’0’ and BCL = ’1’ and the data ...
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The clock pulses will be enabled again when the DU line is pulled low (bit SPU in the IOM_CR register) i.e. the C/I command TIM = "0000" is received by layer 1, or when a non-zero level on the line ...
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SPU = 1 FSC DU DD FSC DU 0 DCL Figure 36 Activation of the IOM-Interface Data Sheet CIC : CIXO = TIM Int IOM -CH1 IOM -CH2 IOM ...
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U Interface PN The layer-1 functions for the U – conversion of the frame structure between IOM and U – conversion from/to binary to/from half-bauded AMI coding – level detection – receive timing recovery – IOM-2 timing synchronous to ...
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LT Binary Value Line Signal t : line delay guard time (5 repetition period (250 s) r Figure 37 U Interface Structure PN Data Sheet ...
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Scrambler/Descrambler B-channel data on the U PN spectrum and to ensure enough pulses are present on the line for a reliable clock extraction to be performed at the downstream end. The SCOUT-P(X) therefore contains a scrambler and descrambler, in ...
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U Transceiver Timing PN The receive PLL uses the 15.36-MHz clock to generate an internal 384-kHz signal which is used to synchronize the PLL to the received U signal as well as the 1.536-MHz double bit clock signal and ...
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Available/Busy Bit The A/B bit has been added to the IOM-2 frame for the operation of a S/T-terminal adapter based on the SBCX PEB 2081 used to transfer the state of the line card HDLC controller indicated ...
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Control The layer-1 activation/deactivation can be controlled by an internal state machine via the IOM-2 C/I0 channel or by software via the microcontroller interface directly. In the default state the internal layer-1 state machine of the ...
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State Transition Diagram The state machine includes all information relevant to the user. The state diagram notation is given in figure 41. The informations contained in the state diagrams are: – State name – U signal transmitted (INFO) (see ...
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Leave for the state “Level Detect” after a signal different to ’INFO 0’ has been recognized on the U PN – Leave for the state “Loop 3” in case C/I = ARL is received. As can be seen from ...
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DC ARL Deactivated i0 AR ARL DI 3) Loop 3 TIM TIM Pending Activation i1w RSY AR Level Detect i0*TO1 ARL2 Synchronized ...
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AR TIM DI AR TIM DI AR TIM DI Figure 43 State Transition Diagram of the Loop 3 State Data Sheet ARL PU ARL Pend. Loop ARL ARL i1*i3 Loop 3 Synchronized RSY ...
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States Reset, Pending Deactivation State after reset or deactivation from the U from the terminal side is possible starting from this state. A ‘DI’-command has to be issued to enter the state ’Deactivated’. Deactivated The U interface is deactivated ...
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Analog Loop 3 Activated After recognition of the looped back info 3 the channels are looped back transparently. Test Mode i After entering test mode initiated by SCP-, SSP-commands. Level Detect, Resynchronization During the first period of receiving info 2 ...
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C/I Commands Command (Upstream) Timing Reset Send Single Pulses Send Continuous Pulses Activate Request Activate Request Loop 3 Deactivation Indication 2.3.5.1.4 Receive Infos on U Name Abbr. Description Info signal on the line Info 2 i2 ...
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Reset RES A low signal on the RST pin or setting the RES_TR bit in the SRES register to ’1’ resets also the layer-1 statemachine. The reset signals should be applied for a minimum of 2 DCL clock cycles. ...
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Transmit Infos Name Abbr. Description Info signal on the line Info 1w i1w Asynchronous wake signal 2-kHz burst rate F0001000100010001000101010100010111111 Code violation in the framing bit Info 1 i1 4-kHz burst signal F000100010001000100010101010001011111M ...
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Example of Activation/Deactivation An example of an activation/deactivation of the U with the time relationships mentioned in the previous chapters is shown in figure 44. µC Interface IOM-2 Interface (C/I) SPU=0, CFS SPU=1 PU SPU=0 AR RSY ...
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External Layer-1 Statemachine Instead of using the integrated layer-1 statemachine it is also possible to implement the layer-1 statemachine completely in software. The internal layer-1 statemachine can be disabled by setting the L1SW bit in the TR_CONF0 register (see ...
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Activation initiated by the Terminal (TE, SCOUT-P(X)) INFO 1W has to be transmitted as long as INFO 0 is received. INFO 0 has to be transmitted thereafter as long as no valid INFO (INFO 2 or INFO 4) is ...
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Activation initiated by the Line Termination LT INFO 0 has to be transmitted as long as no valid INFO (INFO 2 or INFO 4) is received. After reception of INFO 2 or INFO 4 transmission of INFO 1 or ...
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Level Detection Power Down If MODE1.CFS is set to ’0’, the clocks are also provided in power down state, whereas if CFS is set to ’1’ only the analog level detector is active in power down state. All clocks, ...
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Test Functions The SCOUT-P(X) provides several test and diagnostic functions for the transceiver: 2.3.8.1 U Transceiver Test PN Two test loops allow the local or the remote test of the transceiver function. – The local loop (test loop 3) ...
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Transmitter Characteristics The half-bauded pseudo-ternary pulse shaping is achieved with the integrated line driver which drives a binary ’High’ via typical 30 The line driver circuitry is designed to lower the EMI radiation and therefore reducing the expense for ...
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Receiver Characteristics The SCOUT-P(X) covers the electrical requirements of the 4.5 kft on AWG 24 cable and 1 J-Y(ST The receiver consists of a differential input stage, a peak detector and ...
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U Interface Circuitry PN Using a 3.3V power supply a 1:1 transformer has to be connected to the 2 wire U interface. Using a 5V power supply a 2:1 transformer has to be used. Therefore the TRS bit in ...
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HDLC Controller The HDLC controller handles layer-2 functions of the D- channel protocol (LAPD channel protocols. It can access the D or B-channels or any combination of them e.g. 18 bit IDSL data (2B+D) by setting the ...
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Non-Auto Mode (MDS2-0 = ’01x’) Characteristics: Full address recognition with one-byte (MDS = ’010’) or two-byte (MDS = ’011’) address comparison All frames with valid addresses are accepted and the bytes following the address are transferred to the P ...
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Data Reception 3.2.1 Structure and Control of the Receive FIFO 3.2.1.1 General Description The 64-byte cyclic RFIFO buffer has variable FIFO block sizes (thresholds bytes which can be selected by setting the corresponding ...
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The following description of the receive FIFIO operation is illustrated in figure 50 for a RFIFO block size (threshold and 32 bytes. The RFIFO requests service from the microcontroller by setting a bit in the ISTAH register, which ...
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RAM EXMR.RFBS=11 so after the first 4 bytes of a new frame have been stored in the fifo an receive pool full interrupt ISTAH.RPF is set. HDLC Receiver µP RAM HDLC Receiver RSTA The HDLC receiver has written further data ...
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Possible Error Conditions during Reception of Frames If parts of a frame get lost because the receive FIFO is full, the Receive Data Overflow (RDO) byte in the RSTA byte will be set complete frame is lost, ...
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Data Reception Procedure The general procedures for a data reception sequence are outlined in the flow diagram in figure 51 case of RME the last byte in RFIFO contains * the receive status information RSTA Figure ...
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Figure 52 gives an example of an interrupt controlled reception sequence, supposed that a long frame (68 byte) followed by two short frames (12 byte each) is received. The FIFO threshold (block size) is set to 32 byte (EXMR.RFBS = ...
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Receive Frame Structure The management of the received HDLC frames as affected by the different operating modes (see chapter 3.1) is shown in figure 53. Figure 53 Receive Data Flow Data Sheet FLAG ADDR CTRL ...
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The HDLC controller indicates to the host that a new data block can be read from the RFIFO by means of an RPF interrupt (see previous chapter). User data is stored in the RFIFO and information about the received frame ...
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Data Transmission 3.3.1 Structure and Control of the Transmit FIFO 3.3.1.1 General Description The 64-byte cyclic XFIFO buffer has variable FIFO block sizes (thresholds bytes, selectable by the XFBS bit in the EXMR register. There ...
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The XFIFO requests service from the microcontroller by setting a bit in the ISTAH register, which causes an interrupt (XPR, XDU, XMR). The microcontroller can then read the status register STAR (XFW, XDOV), write data in the FIFO and it ...
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Possible Error Conditions during Transmission of Frames If the transmitter sees an empty FIFO, i.e. if the microcontroller does not react quickly enough to an XPR interrupt, an XDU (transmit data underrun) interrupt will be raised. If the HDLC ...
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Data Transmission Procedure The general procedures for a data transmission sequence are outlined in the flow diagram in figure 54. Command XTF Figure 54 Data Transmission Procedure Data Sheet START Transmit N Pool Ready XPR ? Y Write Data ...
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The following description gives an example for the transmission byte frame with a selected block size of 32 byte (EXMR:XFBS=0): • The host writes 32 bytes to the XFIFO, issues an XTF command and waits for an ...
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Transmit Frame Structure The transmission of transparent frames (XTF command) is shown in figure 56. For transparent frames, the whole frame including address and control field must be written to the XFIFO. The host configures whether the CRC is ...
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Extended Transparent Mode This non-HDLC mode is selected by setting MODE2...0 to ’100’. In extended transparent mode fully transparent data transmission/reception without HDLC framing is performed i.e. without FLAG generation/recognition, CRC generation/check, bitstuffing mechanism. This allows user specific protocol ...
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HDLC Controller Interrupts The cause of an interrupt related to the HDLC controller is indicated by the HDLC bit in the ISTA register. This bit points at the different interrupt sources of the HDLC controller part in the ISTAH ...
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Test Functions The following test and diagnostic functions for the D-channel are available: – Digital loop via TLP (Test Loop, TMH register) command bit (figure 58): The TX path of layer 2 is internally connected with the RX path ...
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Codec The codec bridges the gap between the audio world of microphones, earphones, loudspeakers and the PCM digital world by providing a full PCM codec with all the necessary transmit and receive filters. Because the requirements for the codec ...
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The controlling and programming of the various operation modes, configurations and coefficients can be done via the microcontroller interface or the IOM-2 monitor channel and is described in the corresponding interface section. An overview on these programmable parameters can be ...
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Two differential inputs (MIP1/MIN1 and MIP2/MIN2) and one single-ended input (AXI) can be connected to the amplifier AMI via an analog input multiplexer (ATCR.AIMX). The programmable amplifier AMI (ATCR.MIC) provides a coarse gain adjustment range from 0...42dB in 6dB steps. ...
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Figure 61 AFE Attenuation Plan Data Sheet 108 PSB 21391 PSB 21393 Codec 2001-03-07 ...
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Signal Processor (DSP) Description The signal processor (DSP) has been conceived to perform all ITU-T and ETSI (NET33) recommended filtering in transmit and receive paths and is therefore fully compatible to the ITU-T G.712 and ETSI (NET33) specifications. The ...
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Figure 62 Processor Signal Flow Graph Data Sheet ...
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Transmit Signal Processing In the transmit direction a series of decimation filters reduces the sampling rate down to the 8-kHz PCM-rate. These filters attenuate the out-of-band noise by limiting the transmit signal to the voice band. The decimation stages ...
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The GR-gain adjustment stage is digitally programmable from – steps 0.25 dB (– dB and others are also possible). Respectively two bytes are coded in the CRAM to set GR to the desired value. After ...
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Programmable Coefficients for Transmit and Receive This section gives a short overview of important programmable coefficients. For more detailed information a coefficient software package is available (SCOUT MASTER SIPO 21383). Table 10 Description of the programmable Level Adjustment Parameters ...
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Tone Generation The ASP contains a universal tone generator which can be used for tone alerting, call progress tones, DTMF-signals or other audible feedback tones. All the tone generation configurations are programmable in the registers TGCR (Tone Generator Configuration ...
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Figure 64 Signal Flow Graph of the Tone Generation Unit Data Sheet 115 PSB 21391 PSB 21393 Codec 2001-03-07 ...
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Table 12 CRAM Parameters of the Signal and Sequence Generator Parameter # of CRAM Bytes Fn 2/2/2 Gn 1/1/1 Tn 2/2 GDn 1/1 either Note: 0-dB gain setting of G1 ...
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Control Generator Controlling of the generated tone follows the setting of the control bits ET (Enable Tone) and PT (Pulsed Tone) and the CRAM parameters TON and TOFF corresponding table 14 and table 15. Table 14 Control Generator ET ...
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Figure 65 Typical Control Generator Applications 4.3.4 Tone Filter A programmable tone filter can be switched in the tone signal path by setting the ETF (Enable Tone Filter) bit. The tone filter contains a programmable equalizer and a saturation amplifier ...
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The filter parameters (center frequency, bandwidth and attenuation of the stop-band) are programmable by the CRAM parameters listed in Table 16 Table 16 CRAM Parameters of the Tone Filter Parameter # of CRAM Bytes ...
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The two main purposes of the programmable saturation amplification are: • Level balancing of the filtered signal (avoidance of overload effects). • Amplification followed by a saturation (3.14 dBm0) of the incoming signal. This saturation ...
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The pre-emphasis between the high and the low DTMF-frequency groups has to be set with the independent gain parameters (G3 and GD3 resp.) of the trapezoid generators. All generated DTMF-frequencies are guaranteed within a Table 18 DTMF-frequency ...
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Speakerphone Support The speakerphone option of the SCOUT-PX performs all functions required for echo suppression without any external components, just by software. All these operational functions realized by the signal processor are completely parameterized. This technique offers a high ...
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Signal-Processing & Analog Front End SX Signal-Processing SR & Analog Front End Figure 67 Speakerphone Signal Flow Graph of the SCOUT-PX 4.4.1 Attenuation Control Unit The Attenuation Control unit controls the attenuation stages GHX of the transmit and GHR of ...
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Description of the programmable parameters: Parameter # of CRAM Bytes TW 1 ATT 4.4.2 Speakerphone Test Function and Self Adaption For optimizing the speakerphone performance the SCOUT-PX provides following test functions: - The two register ...
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Figure 68 Speech Detector Signal Flow Graph 4.4.3.1 Background Noise Monitor The tasks of the noise monitor are to differentiate voice signals from background noise, even if it exceeds the voice level, and to recognize voice signals without any delay. ...
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A small fade constant (LP2N) enables fast settling down the LP2 to the average noise level after the end of speech recognition. However, a too small time constant for LP2N can cause rapid charging to such a high level that ...
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Description of the programmable speech detector parameters: Parameter # of CRAM Bytes LP1 1 OFF 1 PDS 1 PDN 1 LP2S 1 LP2N 1 LP2L 1 LIMX, LIMR 1 4.4.4 Speech Comparators (SC) Switching from one active mode to another ...
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Speech Comparator at the Acoustic Side (SCAE) In principle, the SCAE works according to the following equation: Being in RX-mode, the speech comparator at the acoustic side controls the switching to TX-mode. Only if the SX-signal is higher than ...
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At the SCAE-input, logarithmic amplifiers compress the signal range. Hence after the required signal processing for controlling the acoustic echo, pure logarithmic levels on both paths are compared. Principally, the main task of the comparator is to control the echo. ...
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Figure 70 Interdependence of GDAE and PDAE According to figure 70, a compromise between the reserve GDAE and the decrement PDAE has to be made: a smaller reserve (GDAE) above the level enhancement GAE requires a longer time to decrease ...
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Description of the programmable parameters: Parameter # of CRAM Bytes GAE 1 GDSAE 1 PDSAE 1 GDNAE 1 PDNAE 1 ETAE 1 4.4.4.2 Speech Comparator at the Line Side (SCLE) Principally, the SCLE works similarly to the SCAE. The formula ...
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Figure 71 Speech Comparator at the Line Side The Gain of the Line Echo (GLE) directly corresponds to the echo return loss of the link. Generally specified to 27 dB. However, the worst case loss can be estimated ...
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Description of the programmable parameters: Parameter # of CRAM Bytes GLE 1 GDSLE 1 PDSLE 1 GDNLE 1 PDNLE 1 ETLE 1 4.4.4.3 Automatic Gain Control of the Transmit Direction (AGCX) Optionally an AGCX is inserted into the transmit path ...
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For reasons of physiological acceptance the AGCX gain is automatically reduced in case of continuous background noise e.g. by ventilators. The reduction is programmed via the NOlSX-parameter. When the noise level increases the threshold determined by NOISX, the amplification will ...
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AGX=0...+18dB AGX Figure 73 Level Diagram For the AGC in Transmit Direction Description of the programmable parameters: Parameter # of CRAM Bytes LGAX 1 COMX 1 AAX 1 AGX 1 AGIX 1 TMLX 1 TMHX 1 NOISX 1 ...
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Automatic Gain Control of the Receive Direction (AGCR) The Automatic Gain Control of the receive direction AGCR (see figure 74) is similar to the transmit AGC. One additional parameter (AAR) offers more flexibility since the AGCR is able to ...
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AGR=0...+18dB AAR=0...-48dB AGR>0 AGR=0 Figure 75 Level Diagram For the AGC in Receive Direction If the speakerphone is in transmit mode, the AGCR is not working; instead the last gain setting is used and the regulation starts with ...
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Description of the programmable parameters: Parameter # of CRAM Bytes LGAR 1 COMR 1 AAR 1 AGIR 1 AGR 1 TMLR 1 TMHR 1 NOISR 1 4.4.6 Speakerphone Coefficient Set Table 19 shows a possible configuration for a speakerphone application ...
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Table 19 Basic Coefficient Set (cont’d) CMD Sequence Coefficient COP_C LIMX, LIMR COP_C OFFX COP_C OFFR COP_C LP2LX COP_C LP2LR COP_C LP1X COP_C LP1R COP_C reserved 00 H COP_D PDSX COP_D PDNX COP_D LP2SX COP_D LP2NX COP_D PDSR COP_D PDNR ...
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Controlled Monitoring A so called “controlled monitoring” can be done when the bit GCR.CME is set. This mode can only be used together with the speakerphone mode (GCR.SP). With CME = ’1’ the attenuation stage GHR is fixed to ...
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Intercommunication: During a running phone call a voice announcement or a query can be switched or added to the desired outputs (handset, loudspeaker or transmit direction) Table 20 Voice Data Manipulation Register Bits DSSR DSS1X, DSS2X: Data Source Data ...
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Test Functions The codec provides several test and diagnostic functions which can be grouped as follows: • All programmable configuration registers and coefficient RAM-locations are readable • Digital loop via PCM-register (DLP) • Digital loop via signal processor (DLS) ...
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Programming of the Codec During initialization of the codec a subset of configuration registers and coefficient RAM (CRAM) locations has to be programmed to set the configuration parameters according to the application and desired features. The codec can be ...
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Description of the Command Word (CMDW) Value after reset CMDW R/W 0 R/W 0: writing to configuration registers or to coefficient RAM 1: reading from configuration registers or from coefficient RAM CMDx Address to internal programmable ...
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Coding of Coefficient Operations (COP) Bit CMD Name COP_0 COP_1 COP_2 COP_3 COP_4 ...
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Direct Programming of the Codec The codec registers (60 H chapter 2.1 and 4.8.2.1). 4.8.2.1 CRAM Back-Up Procedure For the direct access to individual CRAM coefficients via microcontroller a back-up procedure is provided. This ensures that the codec DSP ...
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Access Data Flow Figure 76 CRAM Access Structure Figure 77 Signal Flow of the Back-up Procedure Data Sheet <CBADR_F> <CBADR_E> <CBADR_D> <CBADR_C> <CBADR_B> DCA = ’0’ <CBADR_A> <CBADR_9> <CBADR_8> <CBADR_7> <CBADR_6> <CBADR_5> <CBADR_4> <CBADR_3> <CBADR_2> <CBADR_1> <CBADR_0> DCA = ...
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Reference Tables for the Register and CRAM Locations Table 21 Configuration Registers Address CMDW Register WR/RD SOP_0 60 10 /90 GCR SOP_1 61 11 /91 PFCR SOP_2 62 12 /92 TGCR H H ...
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Table 21 Configuration Registers (cont’d) Address CMDW Register WR/RD SOP_3 63 13 /93 TGSR SOP_4 64 14 /94 ACR SOP_5 65 15 /95 ATCR SOP_6 66 16 /96 ARCR H H ...
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Table 21 Configuration Registers (cont’d) Address CMDW Register WR/RD SOP_8 68 18 /98 DSSR SOP_9 XCR H H -/99 XSR H if MAAR = ’0’ -/99 XSR H if MAAR = ’1’ SOP_A 6A ...
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Table 21 Configuration Registers (cont’d) Address CMDW Register WR/RD SOP_C 6C 1C /9C TFCR SOP_D 6D 1D /9D TMR1 SOP_E 6E 1E /9E TMR2 SOP_F - 1F /9F <DFR> ...
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Table 22 Coefficient RAM (CRAM) Address CMDW Mnemonic Description WR/RD COP_0: Tone generator parameter set / GD1 ...
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Table 22 Coefficient RAM (CRAM) (cont’d) Address CMDW Mnemonic Description WR/RD COP_4: Control generator A3 24 /A4 TON TOFF COP_5: Receive and transmit gain ...
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Table 22 Coefficient RAM (CRAM) (cont’d) Address CMDW Mnemonic Description WR/RD COP_8:Transmit correction filter part 1 to part 4 and receive correction filter part 9 to part / ...
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Table 22 Coefficient RAM (CRAM) (cont’d) Address CMDW Mnemonic Description WR/RD COP_B:Parameter set for transmit and receive speech comparator DF 2B /AB GDSAE PDSAE H DD GDNAE H DC PDNAE H DB GDSLE H DA PDSLE ...
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Table 22 Coefficient RAM (CRAM) (cont’d) Address CMDW Mnemonic Description WR/RD COP_E:Parameter set for transmit AGC F7 2E /AE LGAX COMX H F5 AAX H F4 AGX H F3 TMHX H F2 TMLX H F1 NOISX ...
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Clock Generation Figure 78 shows the clock system of the SCOUT. The oscillator is used to generate a 15.36 MHz clock signal. The DPLL generates the IOM-2 clocks FSC (8 kHz), DCL (1536 kHz) and BCL (768 kHz) synchronous ...
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Jitter 5.1.1 Jitter on IOM-2 The receive PLL readjusts, if the integrator function is enabled (TR_CONF1.RPLL_INTD = ’0’) if six consecutive pulses on the U integrator function is disabled by setting TR_CONF1.RPLL_INTD to ’1’ this is done after the ...
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Reset The SCOUT can be reset completely by a hardware reset (pin RST the integrated undervoltage detection circuit. Additionally each functional block can be reset separately via register SRES. If enabled an exchange awake, subscriber awake, watchdog ...
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Reset Source Selection The internal reset sources C/I code change, EAW and Watchdog can be output at the low active reset pin RSTO/SDS2. The selection of these reset sources can be done with the RSS2,1 bits in the MODE1 ...
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Undervoltage Detection (VDDDET) The integrated undervoltage detection circuit can be enabled or disabled by pinstrapping the VDDDET pin to’V ’ or ’V SS voltage (5V or 3.3 V) and sets RSTO to ’low’ if the supply voltage falls below ...
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Figure 81 Undervoltage Control Timing 6.3 External Reset Input At the active low RST input pin an external reset can be applied forcing the device into the reset state. This external reset signal is additionally fed to the RSTO/SDS2 output. ...
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Pin Behavior during Reset During each reset the reference voltage (V clocks (DCL) keep running. During a reset caused by the undervoltage detection the microcontroller clock (pin MCLK) is stopped. In all other cases the microcontroller clock is running. ...
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Detailed Register Description The register mapping is shown in Figure 82. Figure 82 Register Mapping The register address range from 00-1F address range. The address range 20-2F handler. The register set ranging from 30-3F general configuration registers. The address ...
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HDLC Control Registers, CI Handler Name 7 6 RFIFO XFIFO ISTAH RME RPF MASKH RME RPF STAR XDOV XFW CMDR RMC RRES MODEH MDS2 MDS1 MDS0 EXMR XFBS RFBS TIMR CNT SAP1 SAP2 RBCL RBC7 RBCH 0 0 TEI1 TEI2 ...
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Transceiver, Interrupt, General Configuration Registers NAME 7 6 TR_ DIS_ 0 CONF0 TR TR_ RPLL_ 1 CONF1 INTD TR_ DIS_ 0 CONF2 TX TR_STA RINF TR_CMD XINF ISTATR 0 x MASKTR 0 1 ISTA 0 ST MASK 0 ST MODE1 ...
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IOM Handler (Timeslot , Data Port Selection, CDA Data and CDA Control Register) Name 7 6 CDA10 Controller Data Access Register (CH10) CDA11 Controller Data Access Register (CH11) CDA20 Controller Data Access Register (CH20) CDA21 Controller Data Access Register (CH21) ...
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Name 7 6 CDA1_ CDA2_ IOM Handler (Control Registers, Synchronous Transfer Interrupt Control), MONITOR Handler Name 7 6 CO_CR 0 0 TR_CR 0 0 HCI_CR DPS_ EN_ CI1 CI1 MON_CR DPS EN_ MON SDS1_CR ...
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Name 7 6 SDS_ 0 0 CONF MOR MOX MOSR MDR MER MOCR MRE MRC MSTA 0 0 MCONF 0 0 Codec Configuration Register Name 7 6 GCR SP AGCX AGCR MGCR CME PFCR GX GR TGCR ET DT TGSR ...
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MASK1R MASK2R TFCR 0 0 CCR 0 0 CSR 0 0 Name 7 6 NOP 1 1 After an ISTAH.RME interrupt, the number of received bytes can be obtained by reading the RBCL register. 7.0.1 XFIFO - Transmit FIFO 7 ...
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ISTAH - Interrupt Status Register HDLC Value after reset ISTAH RME RPF RME ... Receive Message End One complete frame of length less than or equal to the defined block size (EXMR.RFBS) or the last part ...
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MASKH - Mask Register HDLC Value after reset MASKH RME RPF Each interrupt source in the ISTAH register can be selectively masked by setting to ’1’ the corresponding bit in MASK. Masked interrupt status bits are ...
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CMDR - Command Register Value after reset CMDR RMC RRES RMC ... Receive Message Complete Reaction to RPF (Receive Pool Full) or RME (Receive Message End) interrupt. By setting this bit, the microcontroller confirms that it ...
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MODEH - Mode Register Value after reset MODEH MDS2 MDS1 MDS0 MDS2-0 ... Mode Select Determines the message transfer mode of the HDLC controller, as follows: MDS2-0 Mode Number of Address Bytes Reserved ...
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RAC ... Receiver Active The HDLC receiver is activated when this bit is set to ’1’ ’0’ the HDLC data is not evaluated in the receiver. DIM2-0 ... Digital Interface Modes These bits define the characteristics of ...
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RFBS RFBS Block Size Bit6 Bit5 Receive FIFO byte byte Note: A change of RFBS will take effect after a receiver command (CMDR.RMC, CMDR.RRES,) has been written SRA … Store Receive Address 0: Receive ...
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CNT ... CNT together with VALUE determine the time period T2 after which a TIN interrupt will be generated in the normal case CNT x 2.048 sec + T1 with VALUE 0.064 sec ...
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RBCL - Receive Frame Byte Count Low Value after reset RBCL RBC7 RBC7-0 ... Receive Byte Count Eight least significant bits of the total number of bytes in a received message. 7.0.11 SAP2 - SAPI2 Register ...
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RBCH - Receive Frame Byte Count High Value after reset RBCH ... Overflow A ’1’ in this bit position indicates a message longer than (2 RBC11-8 ... Receive Byte Count Four most ...
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RSTA - Receive Status Register Value after reset RSTA VFR RDO VFR ... Valid Frame Determines whether a valid frame has been received. The frame is valid (1) or invalid (0). A frame is invalid when ...
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SA1 Number of x Address x Bytes = Number of 0 address 0 Bytes 7.0.15 TEI2 - TEI2 Register Value after reset TEI2 TEI2 ... Terminal Endpoint Identifier In all message ...
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TMH -Test Mode Register HDLC Value after reset TMH 0 0 TLP ... Test Loop The TX path of layer-2 is internally connected with the RX path of layer-2. Data coming from the layer 1 controller ...
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BAS ... Bus Access Status Indicates the state of the TIC-bus: 0: The SCOUT itself occupies the D- and C/I-channel 1: Another device occupies the D- and C/I-channel Note: The CODR0 bits are updated every time a new C/I-code is ...
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CIX0 - Command/Indication Transmit 0 Value after reset CIX0 CODX0 CODX0 ... C/I-Code 0 Transmit Code to be transmitted in the C/I-channel 0. TBA2-0 ... TIC Bus Address Defines the individual address for the SCOUT on ...
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CIX1 - Command/Indication Transmit 1 Value after reset CIX1 CODX1 ... C/I-Code 1 Transmit Bits 7-2 of C/I-channel 1 CICW ... C/I-Channel Width CICW selects between a 4 bit (’0’) and 6 bit (’1’) C/I1 channel ...
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Transceiver, Interrupt and General Configuration Registers 7.1.1 TR_CONF0 - Transceiver Configuration Register Value after reset TR_ DIS_ 0 CONF0 TR DIS_TR ... Disable Transceiver 0: All layer-1 functions are enabled. 1: All layer-1 functions are disabled. ...
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TR_CONF1 - Receiver Configuration Register Value after reset TR_ RPLL_ 1 CONF1 INTD RPLL_INTD ... Receive PLL Integrator Disable (refer to chapter 5.1.1) 0: The integrator function of the receive PLL is enabled 1: The integrator ...
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TR_STA - Transceiver Status Register Value after reset TR_ RINF STA RINF ... Receiver INFO 00: Received INFO 0 01: Received any signal except INFO 2 or INFO 4 10: Received INFO 2 11: Received INFO ...
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TR_CMD - Transceiver Command Register Value after reset TR_ XINF CMD Normally the signals in this register are generated by the layer 1 state machine. If the internal layer 1 state machine is disabled (bit L1SW ...
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ISTATR - Interrupt Status Register Transceiver Value after reset ISTATR 0 x For all interrupts in the ISTATR register following logical states are defined: 0: Interrupt is not activated 1: Interrupt is activated x ... Reserved ...