PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 75

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Figure 33
3.2.13.3 Manchester Encoding
Manchester: In the first half of the bit cell, the physical signal level corresponds to the
logical value of the data bit. At the center of the bit cell this level is inverted. The transmit
clock precedes the receive clock by 90 ° . The bit cell is shifted by 180 ° in comparison with
FM coding.
Figure 34
Data Sheet
Transmit
Clock
Receive
Clock
FM0
FM1
Transmit
Clock
Receive
Clock
Manchester
FM0 and FM1 Data Encoding
Manchester Data Encoding
1
1
1
1
0
0
75
0
0
1
1
Functional Overview
0
0 ITD01810
ITD01809
PEB 20532
PEF 20532
2000-09-14