PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 36

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Table 3
Pin No.
Data Sheet
P-TQFP-
100-3
18
10
Serial Port Pins (cont’d)
Symbol In (I)
RTSA
CTSA
CxDA
TCGA
OSTA
Out (O)
O
I
I
I
I
Function
Request to Send Channel A
The function of this pin depends on the settings of
bits RTS, FRTS in register
In bus configuration, RTS can be programmed to:
– go low during the actual transmission of a
– go low during reception of a data frame.
– stay always high (RTS disabled).
Clear to Send Channel A
A low on the CTSA input enables the transmitter.
Additionally, an interrupt may be issued if a state
transition occurs at the CTSA pin (programmable
feature).
If no ’Clear To Send’ function is required, a pull-
down resistor to V
Collision Data Channel A
In a bus configuration, the external serial bus
must be connected to the corresponding CxDA
pin for collision detection.
A collision is detected whenever a logical ’1’ is
driven on the open drain TxDA output but a
logical ’0’ is detected via CxDA input.
Transmit Clock Gating Channel A (cm 4)
In clock mode 4 these pins are used as Transmit
Clock Gating signals.
If no clock gating function is required, a pull-up
resistor to V
Octet Sync Transmit Channel A (cm 5b)
When the SCC is in the time-slot oriented clock
mode with octet-alignment (clock mode 5b), a
synchronization pulse on this input pin aligns
transmit octets.
frame shifted by one clock period, excluding
collision bits.
36
DD3
is recommended.
SS
is recommended.
CCR1H
Pin Descriptions
.
PEB 20532
PEF 20532
2000-09-14