PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 51

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

3.2.3.2
Externally generated RxCLK is supplied to both the receiver and transmitter. In addition,
a receive strobe can be connected via CD and a transmit strobe via TxCLK pin. These
strobe signals work on a per bit basis. This operating mode can be used in time division
multiplex applications or for adjusting disparate transmit and receive data rates.
Note: In Extended Transparent Mode, the above mentioned strobe signals provide byte
Figure 15
Data Sheet
synchronization (byte alignment).
This means that the strobe signal needs to be detected once only to transmit or
receive a complete byte.
clock mode 1
Clock Mode 1
Clock Mode 1 Configuration
Note: In extended transparent mode the strobe signals need to be detected once only to
transmit or receive a complete byte. Thus byte alignment is provided in this mode.
(rx strobe)
(tx strobe)
RxCLK
TxCLK
RxD
TxD
CD
Ctrl.
Ctrl.
RxCLK
CTS, CxD, TCG
CD, FSC, RCG
TxCLK
RTS
RxD
TxD
51
receive strobe
transmit strobe
V
SS
(enables transmit)
Functional Overview
clock supply
1
PEB 20532
PEF 20532
2000-09-14