PEF 20532 F V1.3 Infineon Technologies, PEF 20532 F V1.3 Datasheet - Page 202

• Manufacturer Part Number: PEF 20532 F V1.3
• Description: IC COMM CTRLR 2CH SER TQFP-100
• Manufacturer: Infineon Technologies

Specifications of PEF 20532 F V1.3

• Function: Serial Optimized Communications Controller
• Interface: ASYNC, BISYNC, HDLC, PPP
• Number Of Circuits: 2
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 50mA
• Power (watts): 150mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 100-LFQFP
• Includes: Automatic Flag Detection and Transmission, Baud Rate Generator, On-Chip Clock Generation, Receive Line Status Detection
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: PEF20532FV1.3X; PEF20532FV13XP; SP000007511

Data Sheet
XAD1 and XAD2 bit fields are valid in HDLC modes with automatic address field
handling only (Automode, Address Mode 1, Address Mode 2). They can be
programmed with one individual address byte which is inserted automatically into the
address field (8 or 16 bit) of a HDLC transmit frame. The function depends on the
selected protocol mode and address field size (bit ’ADM’ in register CCR2L).
XAD1
XAD2
Transmit Address 1
– 2-byte address field:
– 1-byte address field:
Transmit Address 2
– 2-byte address field:
– 1-byte address field:
Bit field
1 must be set to ’0’. According to the ISDN LAP-D protocol, bit 1 is
interpreted as the C/R (COMMAND/RESPONSE) bit. This bit is
manipulated automatically by SEROCCO-M according to the setting
of bit ’CRI’ in register RAH1. The following is the C/R value (on bit 1),
when:
- transmitting COMMANDs:
- transmitting RESPONSEs: ’0’ (if ’CRI’=’1’) ;
(In ISDN LAP-D, the high byte is known as ’SAPI’.)
In accordance with the HDLC protocol, bit ’XAD1_0’ should be set to
’0’, to indicate that the address field contains (at least) one more byte.
According to the X.25 LAP-B protocol,
’COMMAND’ frame.
Bit field
(In ISDN LAP-D, the low byte is known as ’TEI’.)
According to the X.25 LAP-B protocol,
’RESPONSE’ frame.
XAD1
XAD2
constitutes the high byte of the 2-byte address field. Bit
constitutes the low byte of the 2-byte address field.
5-202
’1’ (if ’CRI’=’1’) ;
Register Description (XAD2)
XAD1
XAD2
is the address of a
is the address of a
’0’ (if ’CRI’=’0’)
’1’ (if ’CRI’=’0’)
(hdlc modes)
(hdlc modes)
PEB 20532
PEF 20532
2000-09-14