SI3050-KT Silicon Laboratories Inc, SI3050-KT Datasheet - Page 49

• Manufacturer Part Number: SI3050-KT
• Description: IC VOICE DAA GCI/PCM/SPI 20TSSOP
• Manufacturer: Silicon Laboratories Inc
• Type: Chipsetr

Specifications of SI3050-KT

• Package / Case: 20-TSSOP
• Function: Data Access Arrangement (DAA)
• Interface: PCM, Serial, SPI
• Number Of Circuits: 1
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 8.5mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Includes: Line Voltage Monitor, Loop Current Monitor, Overload Detection, Parallel Handset Detection, Polarity Reversal Detection, TIP and
• Product: Modem Chip
• Supply Voltage (min): 3 V
• Supply Current: 8.5 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power (watts): -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant

The Idle state is achieved by the MX and MR bits being
held inactive (signal is high) for two or more frames.
When a transmission is initiated by a host device, an
active state (signal is low) is present on the downstream
MX bit. This signals to the Si3050 that a transmission
has begun on the Monitor channel and the Si3050
should begin accepting data from host device. The
Si3050, after reading the data on the Monitor channel,
acknowledges the initial transmission by placing the
upstream MR bit in an active state. The data is received
and the upstream MR becomes active in the frame
immediately following the downstream MX becoming
active. The upstream MR then remains active until
either the next byte is received or an end of message is
detected. The end of message is signaled by the
downstream MX being held inactive for two or more
consecutive frames. Receipt of initial data is signaled by
the upstream MR bit’s transitioning from an inactive to
an active state. Upon receiving acknowledgement from
the Si3050 that the initial data is received, the host
device places the downstream MX bit in the inactive
state for one frame and then either transmit another
byte by placing the downstream MX bit in an active state
again, or signal an end of message by leaving the
downstream MX bit inactive for a second frame.
When the host is performing a write command, the host
only manipulates the downstream MX bit, and the
Si3050 only manipulates the upstream MR bit. If a read
command is performed, the host initially manipulates
the downstream MX bit to communicate the command,
but then manipulates the downstream MR bit in
response to the Si3050 responding with the requested
data. Similarly, the Si3050 initially manipulates its
upstream MR bit to receive the read command, and
then manipulates its upstream MX bit to respond with
the requested data. If the host is transmitting data, the
Si3050 always transmits a $FF value on its Monitor data
byte. While the Si3050 is transmitting data, the host
should always transmit a $FF value on its Monitor byte.
If the Si3050 is transmitting data and detects a value
other than a $FF on the downstream Monitor byte, the
Si3050 signals an Abort.
For read and write commands, an initial address must
be specified. The Si3050 responds to a read or a write
command at this address, and then subsequently
increment this address after every register access. In
this manner, multiple consecutive registers can be read
or written in one transmission sequence. By correctly
manipulating the MX and MR bits, a transmission
sequence can continue from the beginning specified
address until an invalid memory location is reached. To
end a transmission sequence, the host processor must
signal an end-of-message (EOM) by placing the
Rev. 1.0
downstream MX and MR bits inactive for two
consecutive frames. The transmission also can be
stopped by the Si3050 by signaling an Abort. This is
signaled by placing the upstream MR bit inactive for at
least two consecutive cycles in response to the
downstream MX bit going active. An abort is signaled by
the Si3050 for the following reasons:
!
!
!
!
When the Si3050 aborts because of an invalid
command sequence, the state of the Si3050 does not
change. If a read or write to an invalid memory address
is attempted, all previous reads or writes in that
transmission sequence are valid up to the read or write
to the invalid memory address. If an EOM is detected
before a valid command sequence is communicated,
the Si3050 returns to the idle state and remains
unchanged.
The data presented to the Si3050 in the downstream
Monitor bits must be present for two consecutive frames
to be considered valid data. The Si3050 checks to
ensure it receives the same data in two consecutive
frames. If not, it does not acknowledge receipt of the
data byte and waits until it does receive two consecutive
identical data bytes before acknowledging to the
transmitter that it received the data. If the transmitter
attempts to signal transmission of a subsequent data
byte by placing the downstream MX bit in an inactive
state while the Si3050 is still waiting to receive a valid
data byte transmission of two consecutive identical data
bytes, the Si3050 signals an abort and ends the
transmission. Figure 43 shows a state diagram for the
Receiver Monitor channel for the Si3050. Figure 44 on
page 51 shows a state diagram for the Transmitter
Monitor channel for the Si3050.
A read or write to an invalid memory address is
attempted
An invalid command sequence is received
A data byte was not received for at least two
consecutive frames
A collision occurs on the Monitor data bytes while
the Si3050 is transmitting data
Si3050
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