C8051F317-GMR Silicon Laboratories Inc, C8051F317-GMR Datasheet - Page 17

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C8051F317-GMR

Manufacturer Part Number
C8051F317-GMR
Description
MCU 8-Bit C8051F31x 8051 CISC 16KB Flash 3.3V 24-Pin QFN EP T/R
Manufacturer
Silicon Laboratories Inc
Datasheet

Specifications of C8051F317-GMR

Package
24QFN EP
Device Core
8051
Family Name
C8051F31x
Maximum Speed
25 MHz
Ram Size
1.25 KB
Program Memory Size
16 KB
Operating Supply Voltage
3.3 V
Data Bus Width
8 Bit
Program Memory Type
Flash
Number Of Programmable I/os
21
Interface Type
I2C/SMBus/SPI/UART
On-chip Adc
17-chx10-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
4

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1.
C8051F31x devices are fully integrated mixed-signal System-on-a-Chip MCUs. Highlighted features are
listed below. Refer to Table 1.1 for specific product feature selection.
With on-chip Power-On Reset, V
are truly stand-alone System-on-a-Chip solutions. The Flash memory can be reprogrammed even in-cir-
cuit, providing non-volatile data storage, and also allowing field upgrades of the 8051 firmware. User soft-
ware has complete control of all peripherals, and may individually shut down any or all peripherals for
power savings.
The on-chip Silicon Labs 2-Wire (C2) Development Interface allows non-intrusive (uses no on-chip
resources), full speed, in-circuit debugging using the production MCU installed in the final application. This
debug logic supports inspection and modification of memory and registers, setting breakpoints, single
stepping, run and halt commands. All analog and digital peripherals are fully functional while debugging
using C2. The two C2 interface pins can be shared with user functions, allowing in-system programming
and debugging without occupying package pins.
Each device is specified for 2.7-to-3.6 V operation over the industrial temperature range (–45 to +85 °C).
The Port I/O and RST pins are tolerant of input signals up to 5 V. The C8051F31x are available in 32-pin
LQFP, 28-pin QFN, and 24-pin QFN packages. See Table 1.1 for ordering part numbers. Note: QFN pack-
ages are also referred to as MLP or MLF packages.
High-speed pipelined 8051-compatible microcontroller core (up to 25 MIPS)
In-system, full-speed, non-intrusive debug interface (on-chip)
True 10-bit 200 ksps 25-channel single-ended/differential ADC with analog multiplexer
(C8051F310/1/2/3/6)
Precision programmable 25 MHz internal oscillator
16 kB (C8051F310/1/6/7) or 8 kB (C8051F312/3/4/5) of on-chip Flash memory
1280 bytes of on-chip RAM
SMBus/I2C, Enhanced UART, and Enhanced SPI serial interfaces implemented in hardware
Four general-purpose 16-bit timers
Programmable Counter/Timer Array (PCA) with five capture/compare modules and Watchdog Timer
function
On-chip Power-On Reset, V
On-chip Voltage Comparators (2)
29/25/21 Port I/O (5 V tolerant)
System Overview
DD
DD
Monitor, and Temperature Sensor
monitor, Watchdog Timer, and clock oscillator, the C8051F31x devices
Rev. 1.7
C8051F310/1/2/3/4/5/6/7
17

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