C8051F317-GMR Silicon Laboratories Inc, C8051F317-GMR Datasheet - Page 106

• Manufacturer Part Number: C8051F317-GMR
• Description: MCU 8-Bit C8051F31x 8051 CISC 16KB Flash 3.3V 24-Pin QFN EP T/R
• Manufacturer: Silicon Laboratories Inc

Specifications of C8051F317-GMR

• Package: 24QFN EP
• Device Core: 8051
• Family Name: C8051F31x
• Maximum Speed: 25 MHz
• Ram Size: 1.25 KB
• Program Memory Size: 16 KB
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 8 Bit
• Program Memory Type: Flash
• Number Of Programmable I/os: 21
• Interface Type: I2C/SMBus/SPI/UART
• On-chip Adc: 17-chx10-bit
• Operating Temperature: -40 to 85 °C
• Number Of Timers: 4

C8051F310/1/2/3/4/5/6/7
9.1.
During power-up, the device is held in a reset state and the RST pin is driven low until V
V
ramp time increases (V
the power-on and V
delay (T
Note: The maximum V
reset before V
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data mem-
ory should be assumed to be undefined after a power-on reset. The V
power-on reset.
9.2.
When a power-down transition or power irregularity causes V
monitor will drive the RST pin low and hold the CIP-51 in a reset state (see Figure 9.2). When V
to a level above V
memory contents are not altered by the power-fail reset, it is impossible to determine if V
the level required for data retention. If the PORSF flag reads ‘1’, the data may no longer be valid. The V
monitor is disabled after power-on resets; however its defined state (enabled/disabled) is not altered by
106
RST
. An additional delay occurs before the device is released from reset; the delay decreases as the V
Power-On Reset
PORDelay
Power-Fail Reset / V
DD
) is typically less than 0.3 ms.
Logic HIGH
Logic LOW
reaches the V
RST
Figure 9.2. Power-On and V
DD
2.70
2.55
2.0
1.0
, the CIP-51 will be released from the reset state. Note that even though internal data
DD
DD
monitor reset timing. For valid ramp times (less than 1 ms), the power-on reset
ramp time is 1 ms; slower ramp times may cause the device to be released from
ramp time is defined as how fast V
/RST
RST
V
RST
DD
level.
Monitor
Power-On
Reset
T
PORDelay
Rev. 1.7
DD
Monitor Reset Timing
DD
DD
ramps from 0 V to V
to drop below V
Monitor
Reset
VDD
DD
monitor is disabled following a
RST
RST
VDD
, the power supply
). Figure 9.2. plots
DD
DD
t
dropped below
settles above
DD
returns
DD
DD