C8051F317-GMR Silicon Laboratories Inc, C8051F317-GMR Datasheet - Page 141
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C8051F317-GMR
Manufacturer Part Number
C8051F317-GMR
Description
MCU 8-Bit C8051F31x 8051 CISC 16KB Flash 3.3V 24-Pin QFN EP T/R
Manufacturer
Silicon Laboratories Inc
Datasheet
1.C8051F310-TB.pdf
(228 pages)
Specifications of C8051F317-GMR
Package
24QFN EP
Device Core
8051
Family Name
C8051F31x
Maximum Speed
25 MHz
Ram Size
1.25 KB
Program Memory Size
16 KB
Operating Supply Voltage
3.3 V
Data Bus Width
8 Bit
Program Memory Type
Flash
Number Of Programmable I/os
21
Interface Type
I2C/SMBus/SPI/UART
On-chip Adc
17-chx10-bit
Operating Temperature
-40 to 85 °C
Number Of Timers
4
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F317-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
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Note:
Bits7–0: Output Configuration Bits for P2.7–P2.0 (respectively): ignored if corresponding bit in regis-
Note:
Bits7–0: P2SKIP[7:0]: Port2 Crossbar Skip Enable Bits.
R/W
R/W
Bit7
Bit7
-
ter P2MDIN is logic 0.
0: Corresponding P2.n Output is open-drain.
1: Corresponding P2.n Output is push-pull.
Only P2.0–P2.5 are associated with Port pins on the C8051F316/7 devices.
These bits select Port pins to be skipped by the Crossbar Decoder. Port pins used as ana-
log inputs (for ADC or Comparator) or used as special functions (VREF input, external oscil-
lator circuit, CNVSTR input) should be skipped by the Crossbar.
0: Corresponding P2.n pin is not skipped by the Crossbar.
1: Corresponding P2.n pin is skipped by the Crossbar.
Only P2.0–P2.3 are associated with the Crossbar.
R/W
R/W
Bit6
Bit6
-
SFR Definition 13.13. P2MDOUT: Port2 Output Mode
SFR Definition 13.14. P2SKIP: Port2 Skip
R/W
R/W
Bit5
Bit5
-
R/W
R/W
Bit4
Bit4
-
Rev. 1.7
R/W
R/W
Bit3
Bit3
C8051F310/1/2/3/4/5/6/7
R/W
R/W
Bit2
Bit2
R/W
R/W
Bit1
Bit1
R/W
R/W
Bit0
Bit0
SFR Address:
SFR Address:
00000000
00000000
Reset Value
Reset Value
0xA6
0xD6
141
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