LMP90077MHENOPB National Semiconductor, LMP90077MHENOPB Datasheet - Page 59

• Manufacturer Part Number: LMP90077MHENOPB
• Description: IC AFE 16BIT 214.6SPS 28-TSSOP
• Manufacturer: National Semiconductor
• Series: -r

Specifications of LMP90077MHENOPB

• Number Of Bits: 16
• Number Of Channels: 2 Differential, 4 Single-Ended
• Power (watts): -
• Voltage - Supply, Analog: 2.85 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: LMP90077MHENOPBTR

DATA_ONLY_2: Data Only Read Control 2 (Address 0x0A)
SPI_DRDYBCN: SPI Data Ready Bar Control (Address 0x11 )
SPI_CRC_CN: CRC Control (Address 0x13 )
[7:3] Reserved
[2:0]
[2:0] Reserved
[7:5] Reserved
[1:0] Reserved
Bit Bit Symbol
Bit Bit Symbol
Bit Bit Symbol
7
6
5
4
3
4
3
2
DATA_ONLY_SZ
SPI_DRDYB_D6
Reserved
CRC_RST
Reserved
FGA_BGCAL
EN_CRC
Reserved
DRDYB_AFT_CRC
Bit Description
-
Number of bytes to be read out in Data Only mode. A value of 0x0 means read one byte
and 0x7 means read 8 bytes.
Default: 0x2
Bit Description
Enable DRDYB on D6
0 (default): D6 is a GPIO
1: D6 = drdyb signal
-
CRC Reset
0 (default): Enable CRC reset on DRDYB deassertion
1: Disbale CRC reset on DRDYB deassertion
-
Gain background calibration
0 (default): Correct FGA gain error. This is useful only if the device is operating in Bg-
calMode2 and ScanMode2 or ScanMode3.
1: Correct FGA gain error using the last known coefficients.
Default - 0x3 (do not change this value)
Bit Description
-
Enable CRC
0 (default): Disable CRC
1: Enable CRC
Default - 0x1 (do not change this value)
DRDYB After CRC
0 (default): DRDYB is deasserted (active high) after ADC_DOUTL is read.
1: DRDYB is deasserted after SPI_CRC_DAT (which follows ADC_DOUTL), is read.
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