LMP90077MHENOPB National Semiconductor, LMP90077MHENOPB Datasheet - Page 37

• Manufacturer Part Number: LMP90077MHENOPB
• Description: IC AFE 16BIT 214.6SPS 28-TSSOP
• Manufacturer: National Semiconductor
• Series: -r

Specifications of LMP90077MHENOPB

• Number Of Bits: 16
• Number Of Channels: 2 Differential, 4 Single-Ended
• Power (watts): -
• Voltage - Supply, Analog: 2.85 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: LMP90077MHENOPBTR

Note that while being in the data first mode, once the data
bytes in the data only read transaction are sent out, the device
is ready to start on any normal (non-data-only) transaction
including the Disable Data First Mode Instruction. The current
status of the data first mode (enabled/disabled status) can be
read back using the Read Mode Status Transaction. This
transaction consists of the Read Mode Status Instruction fol-
lowed by a single data byte (driven by the device). The data
first mode status is available on bit [1] of this data byte.
The data only read transaction allows reading up to eight
consecutive registers, starting from any start address. Usu-
ally, the start address will be the address of the most signifi-
cant byte of conversion data, but it could just as well be any
other address. The start address and number of bytes to be
read during the data only read transaction can be pro-
grammed using the DATA_ONLY_1 AND DATA_ONLY_2
registers respectively.
The upper register address is unaffected by a data only read
transaction. That is, it retains its setting even after encoun-
tering a data only transaction. The data only transaction uses
its own address (including the upper address) from the
DATA_ONLY_1 register. When in the data first mode, the
SCLK must stop high before entering the Data Only Read
If SPI_CRC_DAT read extends beyond the normal DRDYB
deassertion at every 1/ODR seconds, then CRC_RST has to
be set in the SPI Data Ready Bar Control Register. This is
FIGURE 28. Timing Protocol for Reading SPI_CRC_DAT beyond normal DRDYB deassertion at every 1/ODR seconds
FIGURE 27. Timing Protocol for Reading SPI_CRC_DAT
37
Transaction; this transaction should be completed before the
next scheduled DRDYB deassertion.
16.5.8 Cyclic Redundancy Check (CRC)
CRC can be used to ensure integrity of data read from LM-
P900xx. To enable CRC, set EN_CRC high. Once CRC is
enabled, the CRC value is calculated and stored in
SPI_CRC_DAT so that the master device can periodically
read for data comparison. The CRC is automatically reset
when CSB or DRDYB is deasserted.
The CRC polynomial is x
SPI_CRC_DAT register is zero, and the final value is ones-
complemented before it is sent out. Note that CRC computa-
tion only includes the bits sent out on SDO and does not
include the bits of the SPI_CRC_DAT itself; thus it is okay to
read SPI_CRC_DAT repeatedly.
The drdyb signal normally deasserts (active high) every 1/
ODR second. However, this behavior can be changed so that
drdyb deassertion can occur after SPI_CRC_DAT is read, but
not later than normal DRDYB deassertion which occurs at
every 1/ODR seconds. This is done by setting bit
DRDYB_AFT_CRC high.
The timing protocol for CRC can be found in
done to avoid a CRC reset at the DRDYB deassertion.Timing
protocol for reading CRC with CRC_RST set is shown in
ure 28
8
+ x
5
+ x
4
+ 1. The reset value of the
Figure
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27.
30169738
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