LMP90077MHENOPB National Semiconductor, LMP90077MHENOPB Datasheet - Page 4

• Manufacturer Part Number: LMP90077MHENOPB
• Description: IC AFE 16BIT 214.6SPS 28-TSSOP
• Manufacturer: National Semiconductor
• Series: -r

Specifications of LMP90077MHENOPB

• Number Of Bits: 16
• Number Of Channels: 2 Differential, 4 Single-Ended
• Power (watts): -
• Voltage - Supply, Analog: 2.85 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: LMP90077MHENOPBTR

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19.0 Physical Dimensions .................................................................................................................... 61
FIGURE 1. Block Diagram ......................................................................................................................... 2
FIGURE 2. Timing Diagram ...................................................................................................................... 12
FIGURE 3. Simplified VIN Circuitry .............................................................................................................. 21
FIGURE 4. CLK Register Settings ............................................................................................................... 22
FIGURE 5. Digital Filter Response, 1.6775 SPS and 3.355 SPS .......................................................................... 24
FIGURE 6. Digital Filter Response, 6.71 SPS and 13.42 SPS .............................................................................. 24
FIGURE 7. Digital Filter Response at 13.42 SPS ............................................................................................. 25
FIGURE 8. Digital Filter Response, 26.83125 SPS and 53.6625 SPS .................................................................... 25
FIGURE 9. Digital Filter Response 107.325 SPS and 214.65 SPS ........................................................................ 26
FIGURE 10. Digital Filter Response for a 3.5717MHz versus 3.6864 MHz XTAL ...................................................... 26
FIGURE 11. GPIO Register Settings ............................................................................................................ 27
FIGURE 12. Types of Calibration ................................................................................................................ 27
FIGURE 13. BgcalMode2 Register Settings ................................................................................................... 28
FIGURE 14. System Calibration Data-Flow Diagram ......................................................................................... 28
FIGURE 15. Post-calibration Scaling Data-Flow Diagram ................................................................................... 29
FIGURE 16. Burnout Currents .................................................................................................................... 30
FIGURE 17. Burnout Currents Injection for ScanMode3 ..................................................................................... 30
FIGURE 18. Sensor Diagnostic Flags Diagram ............................................................................................... 31
FIGURE 19. Register Read/Write Protocol ..................................................................................................... 32
FIGURE 20. DRDYB Behavior .................................................................................................................... 33
FIGURE 21. DRDYB Behavior for an Incomplete ADC_DOUT Reading .................................................................. 33
FIGURE 22. DrdybCase1 Connection Diagram ............................................................................................... 34
FIGURE 23. Timing Protocol for DrdybCase1 ................................................................................................. 34
FIGURE 24. Timing Protocol for DrdybCase2 ................................................................................................. 35
FIGURE 25. DrdybCase3 Connection Diagram ............................................................................................... 36
FIGURE 26. Timing Protocol for DrdybCase3 ................................................................................................. 36
FIGURE 27. Timing Protocol for Reading SPI_CRC_DAT .................................................................................. 37
FIGURE 28. Timing Protocol for Reading SPI_CRC_DAT beyond normal DRDYB deassertion at every 1/ODR seconds ...... 37
FIGURE 29. Active, Power-Down, Stand-by State Diagram ................................................................................ 38
FIGURE 30. ADC_DOUT vs. VIN of a 16-Bit Resolution (VREF = 5.5V, Gain = 1). .................................................... 39
FIGURE 31. Register-Write Example 1 ......................................................................................................... 40
FIGURE 32. Register-Write Example 2 ......................................................................................................... 40
FIGURE 33. Register-Read Example ........................................................................................................... 41
FIGURE 34. Normal Streaming Example ....................................................................................................... 42
FIGURE 35. Setting up SPI_STREAMCN ...................................................................................................... 43
FIGURE 36. Controlled Streaming Example ................................................................................................... 44
FIGURE 37. Topology #1: 3-wire RTD Using 2 Current Sources ........................................................................... 45
FIGURE 38. Topology #2: 3-wire RTD Using 1 Current Source ............................................................................ 46
FIGURE 39. Thermocouple with CJC ........................................................................................................... 47
TABLE 1. ENOB (Noise Free Resolution) vs. Sampling Rate and Gain at VA = VIO = VREF = 3V ................................. 11
TABLE 2. RMS Noise (µV) vs. Sampling Rate and Gain at VA = VIO = VREF = 3V .................................................... 11
TABLE 3. ENOB (Noise Free Resolution) vs. Sampling Rate and Gain at VA = VIO = VREF = 5V .................................. 11
TABLE 4. RMS Noise (µV) vs. Sampling Rate and Gain at VA = VIO = VREF = 5V .................................................... 11
TABLE 5. Data First Mode Transactions ........................................................................................................ 36
18.4 CHANNEL CONFIGURATION REGISTERS ............................................................................ 52
18.5 CALIBRATION REGISTERS .................................................................................................. 56
18.6 SENSOR DIAGNOSTIC REGISTERS ..................................................................................... 57
18.7 SPI REGISTERS .................................................................................................................. 58
18.8 GPIO REGISTERS ............................................................................................................... 60
List of Figures
List of Tables
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