LMP90077MHENOPB National Semiconductor, LMP90077MHENOPB Datasheet - Page 21

• Manufacturer Part Number: LMP90077MHENOPB
• Description: IC AFE 16BIT 214.6SPS 28-TSSOP
• Manufacturer: National Semiconductor
• Series: -r

Specifications of LMP90077MHENOPB

• Number Of Bits: 16
• Number Of Channels: 2 Differential, 4 Single-Ended
• Power (watts): -
• Voltage - Supply, Analog: 2.85 V ~ 5.5 V
• Voltage - Supply, Digital: 2.7 V ~ 5.5 V
• Package / Case: 28-TSSOP (0.173", 4.40mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: LMP90077MHENOPBTR

16.0 Functional Description
Throughout this datasheet, the LMP90080/LMP90079/
LMP90078/LMP90077 will be referred to as the LMP900xx.
The LMP900xx is a low-power 16-Bit ΣΔ ADC with 4 fully dif-
ferential / 7 single-ended analog channels for the LMP90080/
LMP90079 and 2 full differential / 4 single-ended for the
LMP90078/LMP90077. Its serial data output is two’s comple-
ment format. The output data rate (ODR) ranges from 1.6775
SPS to 214.65 SPS.
The serial communication for LMP900xx is SPI, a syn-
chronous serial interface that operates using 4 pins: chip
select bar (CSB), serial clock (SCLK), serial data in (SDI), and
serial data out / data ready bar (SDO/DRYDYB).
True continuous built-in offset and gain background calibra-
tion is also available to improve measurement accuracy. Un-
like other ADCs, the LMP900xx’s background calibration can
run without heavily impacting the input signal. This unique
technique allows for positive as well as negative gain calibra-
tion and is available at all gain settings.
The registers can be found in
detailed description of the LMP900xx are provided in the fol-
lowing sections.
16.1 SIGNAL PATH
16.1.1 Reference Input (VREF)
The differential reference voltage VREF (VREFP – VREFN)
sets the range for VIN.
The muxed VREF allows the user to choose between VREF1
or VREF2 for each channel. This selection can be made by
Section 18.0
Registers, and a
FIGURE 3. Simplified VIN Circuitry
21
programming the VREF_SEL bit in the CHx_INPUTCN reg-
isters (CHx_INPUTCN: VREF_SEL). The default mode is
VREF1. If VREF2 is used, then VIN6 and VIN7 cannot be
used as inputs because they share the same pin.
Refer to
mation.
16.1.2 Flexible Input MUX (VIN)
LMP900xx provides a flexible input MUX as shown in
3. The input that is digitized is VIN = VINP – VINN; where
VINP and VINN can be any availablie input.
The digitized input is also known as a channel, where
CH = VIN = VINP – VINN. Thus, there are a maximum of 4
differential channels: CH0, CH1, CH2, and CH3 for the
LMP90080/LMP90079. The LMP90078/LMP90077 has 2 dif-
ferential channels: CH0 and CH1 because it does not have
the VIN3, VIN4, and VIN5 pins.
LMP900xx can also be configured single-endedly, where the
common ground is any one of the inputs. There are a maxi-
mum of 7 single-ended channels: CH0, CH1, CH2, CH3, CH4,
CH5, and CH6 for the LMP90080/LMP90079 and 4: CH0,
CH1, CH2, CH3 for the LMP90078/LMP90077.
The input MUX can be programmed in the CHx_INPUTCN
registers. For example on the LMP90080, to program CH0 =
VIN = VIN4 – VIN1, go to the CH0_INPUTCN register and set:
1. VINP = 0x4
2. VINN = 0x1
Section 17.2.2 VREF
for VREF applications infor-
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Figure