MT47H16M16FG-37E Micron Technology Inc, MT47H16M16FG-37E Datasheet - Page 110

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MT47H16M16FG-37E

Manufacturer Part Number
MT47H16M16FG-37E
Description
DRAM Chip DDR2 SDRAM 256M-Bit 16Mx16 1.8V 84-Pin FBGA Tray
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Datasheet

Specifications of MT47H16M16FG-37E

Package
84FBGA
Density
256 Mb
Address Bus Width
15 Bit
Operating Supply Voltage
1.8 V
Maximum Clock Rate
533 MHz
Maximum Random Access Time
0.5 ns
Operating Temperature
0 to 85 °C

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SELF REFRESH
PDF: 09005aef8117c187
256MbDDR2.pdf - Rev. M 7/09 EN
The SELF REFRESH command is initiated when CKE is LOW. The differential clock
should remain stable and meet
refresh mode. The procedure for exiting self refresh requires a sequence of commands.
First, the differential clock must be stable and meet
prior to CKE going back to HIGH. Once CKE is HIGH (
with three clock registrations), the DDR2 SDRAM must have NOP or DESELECT com-
mands issued for
ments is used to apply NOP or DESELECT commands for 200 clock cycles before
applying any other command.
t
XSNR. A simple algorithm for meeting both refresh and DLL require-
110
t
CKE specifications at least 1 ×
Micron Technology, Inc. reserves the right to change products or specifications without notice.
256Mb: x4, x8, x16 DDR2 SDRAM
t
CK specifications at least 1 ×
t
CKE [MIN] has been satisfied
©2003 Micron Technology, Inc. All rights reserved.
t
CK after entering self
SELF REFRESH
t
CK

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