HY27US08281A-TPCB Hynix, HY27US08281A-TPCB Datasheet - Page 7

• Manufacturer Part Number: HY27US08281A-TPCB
• Description: Flash Mem Parallel 3.3V 128M-Bit 16M x 8 10us 48-Pin TSOP-I
• Manufacturer: Hynix

Specifications of HY27US08281A-TPCB

• Package: 48TSOP-I
• Cell Type: NAND
• Density: 128 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3.3 V
• Sector Size: 16KByte x 1024
• Support Of Page Mode: Yes
• Timing Type: Asynchronous
• Operating Temperature: 0 to 70 °C
• Interface Type: Parallel

1.2 PIN DESCRIPTION
Rev 0.6 / Nov. 2005
IO8-IO15(1)
NOTE:
1. For x16 version only
2. A 0.1uF capacitor should be connected between the Vcc Supply Voltage pin and the Vss Ground pin to decouple
the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required
during program and erase operations.
Pin Name
IO0-IO7
WE#
WP#
CE#
RE#
RB#
VCC
CLE
ALE
VSS
PRE
NC
DATA INPUTS/OUTPUTS
The IO pins allow to input command, address and data and to output data during read / program
operations. The inputs are latched on the rising edge of Write Enable (WE#). The I/O buffer float to
High-Z when the device is deselected or the outputs are disabled.
COMMAND LATCH ENABLE
This input activates the latching of the IO inputs inside the Address Register on the Rising edge of
Write Enable (WE#).
ADDRESS LATCH ENABLE
This input activates the latching of the IO inputs inside the Command Register on the Rising edge of
Write Enable (WE#).
CHIP ENABLE
This input controls the selection of the device. When the device is busy CE# low does not deselect
the memory.
WRITE ENABLE
This input acts as clock to latch Command, Address and Data. The IO inputs are latched on the rise
edge of WE#.
READ ENABLE
The RE# input is the serial data-out control, and when active drives the data onto the I/O bus. Data
is valid tREA after the falling edge of RE# which also increments the internal column address counter
by one.
WRITE PROTECT
The WP# pin, when Low, provides an Hardware protection against undesired modify (program /
erase) operations.
READY BUSY
The Ready/Busy output is an Open Drain pin that signals the state of the memory.
SUPPLY VOLTAGE
The VCC supplies the power for all the operations (Read, Write, Erase).
GROUND
NO CONNECTION
To Enable and disable the Lock mechanism and Power On Auto Read. When PRE is a logic high,
Block Lock mode and Power-On Auto-Read mode are enabled, and when PRE is a logic low, Block
Lock mode and Power-On Auto-Read mode are disabled. Power-On Auto-Read mode is available only
on 3.3V device.
Not using LOCK MECHANISM & POWER-ON AUTO-READ, connect it Vss or leave it N.C.
Table 2: Pin Description
128Mbit (16Mx8bit / 8Mx16bit) NAND Flash
Description
HY27US(08/16)281A Series
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