HY27US08281A-TPCB Hynix, HY27US08281A-TPCB Datasheet - Page 11

• Manufacturer Part Number: HY27US08281A-TPCB
• Description: Flash Mem Parallel 3.3V 128M-Bit 16M x 8 10us 48-Pin TSOP-I
• Manufacturer: Hynix

Specifications of HY27US08281A-TPCB

• Package: 48TSOP-I
• Cell Type: NAND
• Density: 128 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3.3 V
• Sector Size: 16KByte x 1024
• Support Of Page Mode: Yes
• Timing Type: Asynchronous
• Operating Temperature: 0 to 70 °C
• Interface Type: Parallel

HY27US(08/16)281A Series
128Mbit (16Mx8bit / 8Mx16bit) NAND Flash
3. DEVICE OPERATION
3.1 Page Read.
Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the
command register along with followed by the three address input cycles. Once the command is latched, it does not
need to be written for the following page read operation.
Three types of operations are available: random read, serial page read and sequential row read.
The random read mode is enabled when the page address is changed. The 528 bytes (x8 device) or 264 word (x16
device) of data within the selected page are transferred to the data registers in less than access random read time tR
(10us). The system controller can detect the completion of this data transfer tR (10us) by analyzing the output of RB#
pin. Once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially puls-
ing RE#. High to low transitions of the RE# clock output the data stating from the selected column address up to the
last column address.
After the data of last column address is clocked out, the next page is automatically selected for sequential row read.
Waiting tR again allows reading the selected page. The sequential row read operation is terminated by bringing CE#
high.
The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. Writing
the Read2 command user may selectively access the spare area of bytes 512 to 527. Addresses A0 to A3 set the start-
ing address of the spare area while addresses A4 to A7 are ignored. Unless the operation is aborted, the page address
is automatically incremented for sequential row
Read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 command
(00h/01h) is needed to move the pointer back to the main area. Figure_10 to 13 show typical sequence and timings
for each read operation.
Devices with automatic read of page0 at power up can be provided on request.
3.2 Page Program.
The device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or
consecutive bytes up to 528 (x8 device), in a single page program cycle. The number of consecutive partial page pro-
gramming operations within the same page without an intervening erase operation must not exceed 1 for main array
and 2 for spare array. The addressing may be done in any random order in a block. A page program cycle consists of a
serial data loading period in which up to 528 bytes (x8 device) or 264 word (x16 device) of data may be loaded into
the page register, followed by a non-volatile programming period where the loaded data is programmed into the
appropriate cell. Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation,
please refer to Figure_27.
The data-loading sequence begins by inputting the Serial Data Input command (80h), followed by the three address
input cycles and then serial data loading. The Page Program confirm command (10h) starts the programming process.
Writing 10h alone without previously entering the serial data will not initiate the programming process. The internal
Program Erase Controller automatically executes the algorithms and timings necessary for program and verify, thereby
freeing the system controller for other tasks. Once the program process starts, the Read Status Register command
may be entered, with RE# and CE# low, to read the status register. The system controller can detect the completion of
a program cycle by monitoring the RB# output, or the Status bit (I/O 6) of the Status Register. Only the Read Status
command and Reset command are valid while programming is in progress. When the Page Program is complete, the
Write Status Bit (I/O 0) may be checked Figure_14.
The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command reg-
ister remains in Read Status command mode until another valid command is written to the command register.
Rev 0.6 / Nov. 2005
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