HY27US08281A-TPCB Hynix, HY27US08281A-TPCB Datasheet - Page 13

• Manufacturer Part Number: HY27US08281A-TPCB
• Description: Flash Mem Parallel 3.3V 128M-Bit 16M x 8 10us 48-Pin TSOP-I
• Manufacturer: Hynix

Specifications of HY27US08281A-TPCB

• Package: 48TSOP-I
• Cell Type: NAND
• Density: 128 Mb
• Architecture: Sectored
• Block Organization: Symmetrical
• Typical Operating Supply Voltage: 3.3 V
• Sector Size: 16KByte x 1024
• Support Of Page Mode: Yes
• Timing Type: Asynchronous
• Operating Temperature: 0 to 70 °C
• Interface Type: Parallel

HY27US(08/16)281A Series
128Mbit (16Mx8bit / 8Mx16bit) NAND Flash
3.5 Read Status Register.
The device contains a Status Register which may be read to find out whether read, program or erase operation is com-
pleted, and whether the program or erase operation is completed successfully. After writing 70h command to the com-
mand register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge of CE# or
RE#, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple
memory connections even when RB# pins are common-wired. RE# or CE# does not need to be toggled for updated
status. Refer to table 13 for specific Status Register definitions. The command register remains in Status Read mode
until further commands are issued to it. Therefore, if the status register is read during a random read cycle, a read
command (00h or 50h) should be given before sequential page read cycle.
3.6 Read ID.
The device contains a product identification mode, initiated by writing 90h to the command register, followed by an
address input of 00h. Two read cycles sequentially output the manufacturer code (ADh), the device code. The com-
mand register remains in Read ID mode until further commands are issued to it. Figure 17 shows the operation
sequence, while tables 17 explain the byte meaning.
3.7 Reset.
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state
during random read, program or erase mode, the reset operation will abort these operations. The contents of memory
cells being altered are no longer valid, as the data will be partially programmed or erased. The command register is
cleared to wait for the next command, and the Status Register is cleared to value E0h when WP# is high. Refer to
table 12 for device status after reset operation. If the device is already in reset state a new reset command will not be
accepted by the command register. The RB# pin transitions to low for tRST after the Reset command is written. Refer
to figure 23.
Rev 0.6 / Nov. 2005
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