GS840E18AT-166 GSI TECHNOLOGY, GS840E18AT-166 Datasheet - Page 20

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GS840E18AT-166

Manufacturer Part Number
GS840E18AT-166
Description
SRAM Chip Sync Dual 3.3V 4M-Bit 256K x 18 8.5ns/3.5ns 100-Pin TQFP Tray
Manufacturer
GSI TECHNOLOGY
Datasheet

Specifications of GS840E18AT-166

Package
100TQFP
Timing Type
Synchronous
Density
4 Mb
Data Rate Architecture
SDR
Typical Operating Supply Voltage
3.3 V
Number Of I/o Lines
18 Bit
Number Of Ports
2
Number Of Words
256K
AC Electrical Characteristics
Notes:
1.
2.
Rev: 1.12 10/2004
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Through
Pipeline
Flow
These parameters are sampled and are not 100% tested
ZZ is an asynchronous signal. However, In order to be recognized on any given clock cycle, ZZ must meet the specified setup and hold
times as specified above.
Clock to Output in High-Z
Clock to Output in Low-Z
Clock to Output in Low-Z
Clock to Output Invalid
Clock to Output Invalid
Clock to Output Valid
Clock to Output Valid
G to output in High-Z
G to output in Low-Z
Clock Cycle Time
Clock Cycle Time
Clock HIGH Time
G to Output Valid
Clock LOW Time
ZZ setup time
ZZ hold time
ZZ recovery
Parameter
Setup time
Hold time
Symbol
tOHZ
tOLZ
tZZS
tZZH
tKQX
tKQX
tZZR
tHZ
tLZ
tLZ
tKC
tKQ
tKC
tKQ
tKH
tOE
tKL
tS
tH
1
1
1
2
1
2
1
Min
5.3
1.5
1.5
8.5
3.0
3.0
1.3
1.5
1.5
1.5
0.5
20
0
5
1
-190
20/31
Max
3.0
7.5
3.0
3.0
3.0
Min
5.5
1.5
1.5
9.0
3.0
3.0
1.3
1.5
1.5
1.5
0.5
20
0
5
1
-180
Max
3.0
8.0
3.2
3.2
3.2
GS840E18/32/36AT/B-190/180/166/150/100
10.0
Min
6.0
1.5
1.5
3.0
3.0
1.3
1.5
1.5
1.5
0.5
20
0
5
1
-166
Max
3.5
8.5
3.5
3.5
3.5
1.5
12.0
Min
6.7
1.5
3.0
3.0
1.3
1.5
1.5
1.5
0.5
20
0
5
1
-150
Max
10.0
3.8
3.8
3.8
3.8
© 1999, GSI Technology
15.0
Min
1.5
1.5
3.0
3.0
1.3
1.5
1.5
2.0
0.5
20
10
0
5
1
-100
Max
12.0
4.5
5
5
5
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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